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User's Manual
PD78014, 78014Y SUBSERIES
8-BIT SINGLE-CHIP MICROCONTROLLERS
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PD78011B PD78012B PD78013 PD78014 PD78P014 PD78011B (A) PD78012B (A) PD78013 (A) PD78014 (A)
PD78011BY PD78012BY PD78013Y PD78014Y PD78P014Y
Document No. U10085EJ7V0UM00 (7th edition) Date Published October 1997 N
(c)
Printed in Japan
1992
1
[MEMO]
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2
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the
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devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
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FIP, IEBus, and QTOP are trademarks of NEC Corporation. Microsoft and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation. HP9000 Series 300, HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. Ethernet is a trademark of XEROX Corporation.
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NEWS, NEWS-OS are trademarks of SONY Corporation. OSF/Motif is a trademark of Open Softwear Foundation, Inc. TRON is an abbreviation of The Real-time Operating system Nucleus. ITRON is an abbreviation of Industrial TRON.
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
License not needed
: PD78P014DW, 78P014YDW
The customer must judge the need for license:
PD78011BCW-xxx, 78011BGC-xxx-AB8, PD78011BCW(A)-xxx, 78011BGC(A)-xxx-AB8, PD78011BYCW-xxx, 78011BYGC-xxx-AB8, PD78012BCW-xxx, 78012BGC-xxx-AB8, PD78012BCW(A)-xxx, 78012BGC(A)-xxx-AB8, PD78012BYCW-xxx, 78012BYGC-xxx-AB8, PD78013CW-xxx, 78013GC-xxx-AB8, PD78013CW(A)-xxx, 78013GC(A)-xxx-AB8, PD78013YCW-xxx, 78013YGC-xxx-AB8, PD78014CW-xxx, 78014GC-xxx-AB8, PD78014CW(A)-xxx, 78014GC(A)-xxx-AB8, PD78014YCW-xxx, 78014YGC-xxx-AB8, PD78P014CW, 78P014GC-AB8, PD78P014YCW, 78P014YGC-AB8
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Caution Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
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The information in this document is subject to change without notice. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, antidisaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M7 96.5
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Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
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NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
NEC do Brasil S.A.
Cumbica-Guarulhos-SP, Brasil Tel: 011-6465-6810 Fax: 011-6465-6829
J97. 8
6
Main Revisions in This Edition
Pages p. 43, 44, 56, 57 Description The following subseries were added in sections 1.6 and 2.6, "78K/0 Series Expansion."
PD78075B, 78075BY, 780018, 780018Y, 780058, 780058Y, 780034, 780034Y, 780024, 780024Y,
78014H, 780964, 780924, 780228, 78044H, 78044F, 78098B, 780973 Subseries p. 137 through 141 The illustrations were modified in Figures 6-6 and 6-8, "P20, P21, P23 to P26 Block Diagrams", Figures 6-7 and 6-9, "P22 and P27 Block Diagrams", and Figure 6-10, "P30 to P37 Block Diagrams". p. 215, 219 p. 264, 321 p. 271, 330 Figures 9-10 and 9-13, "Square Wave Output Operation Timings" were added. Cautions were added in sections 15.1 and 16.1, "Serial Interface Channel 0 Configuration". Cautions were added in sections 15.3 and 16.3, "Serial Interface Channel 0 Control Register (2) Serial operating mode register 0 (CSIM0)". p. 287, 310, 348, 371 Cautions were added in sections 15.4.3 and 16.4.3, "(2) (a) Bus release signal (REL), (b) Command signal (CMD), (11) Cautions on SBI mode". p. 421 p. 439 (3) MSB/LSB switching as the start bit was added in section 17.4.2, "3-wire serial I/O mode operation". (3) (d) Busy control option, (e) Busy & strobe control option, and (f) Bit slippage detection function in section 17.4.3 of the former edition were changed to (4) Synchronization control and the description was improved. p. 495 Caution was added in Table 22-1, "Differences between PD78P014, 78P014Y, and Mask ROM Version". p. 521
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APPENDIX A DIFFERENCES BETWEEN PD78014, 78014H, AND 78018F SUBSERIES was added. Windows compatible 5-inch FD products was erased in APPENDIX B DEVELOPMENT TOOLS. The following products were changed from "Under development" to "Developed". IE-78000-R-A ID78K0
p. 528, 529 p. 527, 529
The mark
shows major revised points.
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[MEMO]
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PREFACE
Readers
This manual has been prepared for user engineers who want to understand the functions of the
PD78014, 78014Y Subseries and design and develop its application systems and programs.
Target subseries are as follows. * PD78014 Subseries : PD78011B, 78012B, 78013, 78014, 78P014
PD78011B(A), 78012B(A), 78013(A), 78014(A)
* PD78014Y Subseries: PD78011BY, 78012BY, 78013Y, 78014Y, 78P014Y Caution Of the above members, the PD78P014DW, 78P014YDW should be used only for experiment or function evaluation, because they are not intended for use in equipment that will be mass-produced and do not have enough reliability. Purpose This manual is intended to help users understand the functions described following the Organization below. Organization The PD78014, 78014Y Subseries manual is separated into two parts: this manual and Instructions (common to the 78K/0 Series)
PD78014, 78014Y SUBSERIES
USER'S MANUAL
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78K/0 SERIES USER'S MANUAL - Instructions - * CPU functions * Instruction set * Explanation of each instruction
(This manual) * Pin functions * Internal block functions * Interrupts * Miscellaneous on-chip peripheral functions How to Read This Manual
Before reading this manual, you must have general knowledge of electric and logic circuits and microcontrollers. When using this manual as the one for the PD78011B(A), 78012B(A), 78013(A), 78014 (A): The PD78011, 78012B, 78013, 78014 and the PD78011B(A), 78012B(A), 78013(A), 78014(A) are different only in quality grade. For products (A), regard the product name as follows.
PD78011B PD78011B(A) PD78013 PD78013(A)
PD78012B PD78012B(A) PD78014 PD78014(A)
To understand the functions in general: Read this manual in the order of the contents. To interpret the register format: For the circled bit number, the bit name is defined as a reserved word in RA78K/0, and in CC78K/0, already defined in the header file named sfrbit.h.
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To confirm the details of the register whose register name is known: Refer to APPENDIX D REGISTER INDEX. For the details of the PD78014, 78014Y Subseries instruction function: Refer to the 78K/0 SERIES USER'S MANUAL, Instructions. (IEU1372). For the electrical specifications of the PD78014, 78014Y Subseries: Refer to Data Sheet. For the application examples of PD78014, 78014Y Subseries functions: Refer to Application Note.
Caution The use examples in the manual apply to the general electric devices of the standard quality grade. To use the use examples in the manual for applications requiring the special quality grade, examine the quality grade of the actually used parts and circuits.
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Chapter composition
This manual describes points for which functions of PD78014 and PD78014Y Subseries are not same in different chapters. The chapters explaining the subseries are shown in the table below. If you use one of the subseries, you should read the chapters with marks.
Chapter Chapter 1 Outline (PD78014 Subseries) Chapter 2 Outline (PD78014Y Subseries) Chapter 3 Pin Function (PD78014 Subseries) Chapter 4 Pin Function (PD78014Y Subseries) Chapter 5 CPU Architecture Chapter 6 Port Functions Chapter 7 Clock Generator Chapter 8 16-bit Timer/Event Counter Chapter 9 8-bit Timer Event Counter Chapter 10 Watch Timer Chapter 11 Watchdog Timer Chapter 12 Clock Output Control Circuit Chapter 13 Buzzer Output Control Circuit Chapter 14 A/D Converter Chapter 15 Serial Interface Channel 0 (PD78014 Subseries)
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PD78014
Subseries -- -- --
PD78014Y
Subseries -- -- --
Chapter 16 Serial Interface Channel 0 (PD78014Y Subseries) Chapter 17 Serial Interface Channel 1 Chapter 18 Interrupt Functions and Test Function Chapter 19 External Device Expansion Function Chapter 20 Standby Function Chapter 21 Reset Function Chapter 22 PD78P014, 78P014Y Chapter 23 Instruction Set
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Differences between PD78014 Subseries and PD78014Y Subseries The PD78014 Subseries and PD78014Y Subseries differ in some of the serial interface channel 0 modes as shown below.
Mode of Serial Interface Channel 0 3-wire serial I/O mode 2-wire serial I/O mode SBI (serial bus interface) mode I2C (Inter IC) bus mode : available -- : not available
PD78014
Subseries --
PD78014Y
Subseries
Legend
Data representation weight : Active low representations : Note Caution Remark Numeral representations : : : :
High digits on the left and low digits on the right xxx (top bar over pin or signal name) Description of "Note" in the text Information requiring particular attention Additionally explanatory material Binary ................ xxxx or xxxxB Decimal ............. xxxx Hexadecimal ..... xxxxH
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Related Documents
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such.
*
Documents related to devices
Document Name Document Number Japanese Version English Version This manual IC-3179 IC-3098 IC-3411 IC-3405 IC-3180 -- IEU-1372 -- -- IEA-1301 IEA-1288 IEA-1289 U10085J IC-8201 IC-8111 IC-8874 IC-8573 IC-8572 IEM-5527 U12326J U10903J U10904J IEA-744 Basic (I) Floating Point Operation Program IEA-715 IEA-718
PD78014, 78014Y Subseries User's Manual PD78011B, 78012B, 78013, 78014 Data Sheet PD78P014 Data Sheet PD78011B(A), 78012B(A), 78013(A), 78014(A) Data Sheet PD78011BY, 78012BY, 78013Y, 78014Y Data Sheet PD78P014Y Data Sheet PD78014, 78014Y Series Special Function Register Table
78K/0 Series User's Manual -- Instruction 78K/0 Series Instruction Set 78K/0 Series Instruction Table
PD78014 Series Application Note
78K/0 Series Application Note
12
*
Document related to development tools (User's Manual)
Document name RA78K Series Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor RA78K0 Assembler Package Operation Assembly Language Structured Assembly Language CC78K Series C Compiler Operation Language CC78K0 C Compiler Operation Language CC78K/0 C Compiler Application Note CC78K Series Library Source File PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOSTM based) PG-1500 Controller IBM PC Series (PC DOSTM) based) IE-78000-R IE-78000-R-A IE-78000-R-BK IE-78014-R-EM IE-78014-R-EM-A Programming know-how
Document Number
Japanese Version EEU-809 EEU-815 U12323J U11802J U11801J U11789J EEU-656 EEU-655 U11517J U11518J EEA-618 U12322J U11940J EEU-704 EEU-5008 EEU-810 U11376J EEU-867 EEU-805 EEU-962 EEU-986 English Version EEU-1399 EEU-1404 EEU-1402 U11802E U11801E U11789E EEU-1280 EEU-1284 U11517E U11518E EEA-1208 -- EEU-1335 EEU-1291 U10540E U11376E U10057E EEU-1427 EEU-1400 EEU-1487 U10332E U10181E U10092E -- U11539E U11649E -- -- U10539E U11279E
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EP-78240 SM78K0 System Simulator WindowsTM SM78 Series System Simulator ID79K0 Integrated Debugger EWS based ID78K0 Integrated Debugger PC based ID78K0 Integrated Debugger Windows based SD78K/0 Screen Debugger PC-9800 Series (MS-DOS) based SD78K/0 Screen Debugger IBM PC/ATTM (PC DOS) based Reference External Part User Open Interface Specification Reference Reference Guides Basic Reference Basic Reference
U10181J U10092J U11151J U11539J U11649J EEU-852 U10952J EEU-5024 U11279J
*
Documents related to embedded software (User's Manual)
Document Name 78K/0 Series Real-Time OS Basic Install 78K/0 Series OS MX78K0 Fuzzy Knowledge Data Creation Tool 78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System (Translator) 78K/0 Series Fuzzy Inference Development Support System (Fuzzy Inference Module) 78K/0 Series Fuzzy Inference Development Support System (Fuzzy Inference Debugger) Basic
Document Number
Japanese Version U11537J U11536J U12257J EEU-829 EEU-862 EEU-858 EEU-921 English Version U11537E U11536E -- EEU-1438 EEU-1444 EEU-1441 EEU-1458
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*
Other related documents
Document Name IC Package Manual Semiconductor Device Mounting Technology Manual Quality Grade of NEC Semiconductor Devices Reliability and Quality Control of NEC Semiconductor Devices Electrostatic Discharge (ESD) Test Guide to Quality Assurance of Semiconductor Devices Guide to Microcontroller-Related Products - Other Manufacturers Document Number Japanese Version C10943X C10535J C11531J C10983J MEM-539 C11893J U11416J C10535E C11531E C10983E -- MEI-1202 -- English Version
Caution The contents of the above documents are subject to change without notice. Be sure to use the latest edition for designing.
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CONTENTS
CHAPTER 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
OUTLINE (PD78014 Subseries).........................................................................
35 35 36 36 37 38 43 45 46 47 48 49 49 50 50 50 51 56 58 59 61 63 63
63 66
Features .......................................................................................................................... Application Fields .......................................................................................................... Ordering Information ..................................................................................................... Quality Grade ................................................................................................................. Pin Configurations (Top View) ..................................................................................... 78K/0 Series Expansion ................................................................................................ Block Diagram ................................................................................................................ Outline of Function ........................................................................................................ Differences among PD78011B, 78012B, 78013, 78014 and PD78011B(A), 78012B(A), 78013(A), 78014(A) .................................................................................... 1.10 Mask Options .................................................................................................................. CHAPTER 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 OUTLINE (PD78014Y Subseries) ......................................................................
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Features .......................................................................................................................... Application Fields .......................................................................................................... Ordering Information ..................................................................................................... Quality Grade ................................................................................................................. Pin Configurations (Top View) ..................................................................................... 78K/0 Series Expansion ................................................................................................ Block Diagram ................................................................................................................ Outline of Function ........................................................................................................ Mask Options .................................................................................................................. PIN FUNCTION (PD78014 Subseries) ..............................................................
CHAPTER 3 3.1
Pin Function List ............................................................................................................
3.1.1 3.1.2 Normal operating mode pins ............................................................................................. PROM programming mode pins (PD78P014 only) ........................................................ P00 to P04 (Port 0) ............................................................................................................ P10 to P17 (Port 1) ............................................................................................................ P20 to P27 (Port 2) ............................................................................................................ P30 to P37 (Port 3) ............................................................................................................ P40 to P47 (Port 4) ............................................................................................................ P50 to P57 (Port 5) ............................................................................................................ P60 to P67 (Port 6) ............................................................................................................ AVREF ................................................................................................................................... AVDD ....................................................................................................................................
3.2
Description of Pin Functions .......................................................................................
3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.2.8 3.2.9
67
67 68 69 70 71 71 72 72 72 72 72 72 73
3.2.10 AVSS .................................................................................................................................... 3.2.11 RESET ................................................................................................................................ 3.2.12 X1 and X2 ........................................................................................................................... 3.2.13 XT1 and XT2 ......................................................................................................................
15
3.2.14 VDD ...................................................................................................................................... 3.2.15 VSS ....................................................................................................................................... 3.2.16 VPP (PD78P014 only) ....................................................................................................... 3.2.17 IC (Mask ROM version only) .............................................................................................
73 73 73 73
3.3
Input/Output Circuit and Recommended Connection of Unused Pins .................. PIN FUNCTION (PD78014Y Subseries) ............................................................
74 79 79
79 82
CHAPTER 4 4.1
Pin Function List ............................................................................................................
4.1.1 4.1.2 Normal operating mode pins ............................................................................................. PROM programming mode pins (PD78P014Y only) ...................................................... P00 to P04 (Port 0) ............................................................................................................ P10 to P17 (Port 1) ............................................................................................................ P20 to P27 (Port 2) ............................................................................................................ P30 to P37 (Port 3) ............................................................................................................ P40 to P47 (Port 4) ............................................................................................................ P50 to P57 (Port 5) ............................................................................................................ P60 to P67 (Port 6) ............................................................................................................ AVREF ................................................................................................................................... AVDD ....................................................................................................................................
4.2
Description of Pin Functions .......................................................................................
4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.2.8 4.2.9
83
83 84 85 86 87 87 88 88 88 88 88 88 89 89 89 89 89
4.2.10 AVSS .................................................................................................................................... 4.2.11 RESET ................................................................................................................................ 4.2.12 X1 and X2 ...........................................................................................................................
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4.2.13 XT1 and XT2 ...................................................................................................................... 4.2.14 VDD ...................................................................................................................................... 4.2.15 VSS ....................................................................................................................................... 4.2.16 VPP (PD78P014Y only) ..................................................................................................... 4.2.17 IC (Mask ROM versions only) ...........................................................................................
4.3
Input/Output Circuit and Recommended Connection of Unused Pins .................. CPU ARCHITECTURE ...........................................................................................
90 95 95
CHAPTER 5 5.1
Memory Spaces ..............................................................................................................
5.1.1 5.1.2 5.1.3 5.1.4
Internal program memory space ....................................................................................... 100 Internal data memory space .............................................................................................. 101 Special function register (SFR) area ................................................................................. 101 External memory space ..................................................................................................... 101 Control registers ................................................................................................................. 102 General registers ................................................................................................................ 106 Special function register (SFR) ......................................................................................... 108 Relative addressing ............................................................................................................ 111 Immediate addressing ........................................................................................................ 112 Table indirect addressing ................................................................................................... 113 Register addressing ........................................................................................................... 114
5.2
Processor Registers ...................................................................................................... 102
5.2.1 5.2.2 5.2.3
5.3
Instruction Address Addressing ................................................................................. 111
5.3.1 5.3.2 5.3.3 5.3.4
16
5.4
Operand Address Addressing ..................................................................................... 115
5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.4.8 5.4.9 Data memory addressing ................................................................................................... 115 Implied addressing ............................................................................................................. 120 Register addressing ........................................................................................................... 121 Direct addressing ............................................................................................................... 122 Short direct addressing ...................................................................................................... 123 Special function register (SFR) addressing ...................................................................... 125 Register indirect addressing .............................................................................................. 126 Based addressing ............................................................................................................... 127 Based indexed addressing ................................................................................................ 128
5.4.10 Stack addressing ................................................................................................................ 128
CHAPTER 6 6.1 6.2
PORT FUNCTIONS ................................................................................................ 129
Port Functions ................................................................................................................ 129 Port Block Diagram ....................................................................................................... 134
6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 Port 0 .................................................................................................................................. 134 Port 1 .................................................................................................................................. 136 Port 2 (PD78014 Subseries) ............................................................................................ 137 Port 2 (PD78014Y Subseries) ......................................................................................... 139 Port 3 .................................................................................................................................. 141 Port 4 .................................................................................................................................. 142 Port 5 .................................................................................................................................. 143 Port 6 .................................................................................................................................. 144
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6.3 6.4
Port Function Control Registers ................................................................................. 146 Port Function Operations ............................................................................................. 152
6.4.1 6.4.2 6.4.3 Writing to input/output port ................................................................................................ 152 Reading from input/output port .......................................................................................... 152 Operations on input/output port ......................................................................................... 153
6.5
Mask Options .................................................................................................................. 154 CLOCK GENERATOR ........................................................................................... 155 155 155 157 160
CHAPTER 7 7.1 7.2 7.3 7.4
Clock Generator Functions .......................................................................................... Clock Generator Configuration .................................................................................... Clock Generator Control Register ............................................................................... System Clock Oscillator ...............................................................................................
7.4.1 7.4.2 7.4.3 7.4.4
Main system clock oscillator .............................................................................................. 160 Subsystem clock oscillator ................................................................................................. 160 Divider ................................................................................................................................. 163 When no subsystem clocks are used ............................................................................... 163 Main system clock operations ........................................................................................... 165 Subsystem clock operations .............................................................................................. 167 Time required for switchover between system clock and CPU clock .............................. 168 System clock and CPU clock switching procedure .......................................................... 169
7.5
Clock Generator Operations ........................................................................................ 164
7.5.1 7.5.2
7.6
Changing System Clock and CPU Clock Settings .................................................... 168
7.6.1 7.6.2
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CHAPTER 8 8.1 8.2 8.3 8.4 8.5
16-BIT TIMER/EVENT COUNTER ........................................................................ 171 Timer in PD78014, 78014Y Subseries ..................................... Counter Functions ....................................................................... Counter Configuration ................................................................ Counter Control Registers ......................................................... Counter Operations ..................................................................... 171 172 173 178 186
Outline of On-chip 16-Bit Timer/Event 16-Bit Timer/Event 16-Bit Timer/Event 16-Bit Timer/Event
8.5.1 8.5.2 8.5.3 8.5.4 8.5.5
Interval timer operations .................................................................................................... 186 PWM output operations ..................................................................................................... 188 Pulse width measurement operations ............................................................................... 190 External event counter operation ...................................................................................... 193 Square-wave output operation .......................................................................................... 195
8.6
16-Bit Timer/Event Counter Operating Precautions ................................................. 196 8-BIT TIMER/EVENT COUNTER .......................................................................... 199
CHAPTER 9 9.1
8-Bit Timer/Event Counter Functions ......................................................................... 199
9.1.1 9.1.2 8-bit timer/event counter mode .......................................................................................... 199 16-bit timer/event counter mode ........................................................................................ 202
9.2 9.3 9.4
8-Bit Timer/Event Counter Configuration .................................................................. 204 8-Bit Timer/Event Counter Control Registers ............................................................ 207 8-Bit Timer/Event Counter Operations ....................................................................... 212
9.4.1 9.4.2 8-bit timer/event counter mode .......................................................................................... 212 16-bit timer/event counter mode ........................................................................................ 216
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9.5
Cautions on 8-Bit Timer/Event Counter Operating ................................................... 220
CHAPTER 10 WATCH TIMER ...................................................................................................... 223 10.1 10.2 10.3 10.4 Watch Watch Watch Watch Timer Timer Timer Timer Functions ................................................................................................. Configuration .......................................................................................... Control Registers ................................................................................... Operations ............................................................................................... 223 224 224 228
10.4.1 Watch timer operation ........................................................................................................ 228 10.4.2 Interval timer operation ...................................................................................................... 229
CHAPTER 11 WATCHDOG TIMER .............................................................................................. 231 11.1 11.2 11.3 11.4 Watchdog Watchdog Watchdog Watchdog Timer Timer Timer Timer Functions .......................................................................................... Configuration ................................................................................... Control Registers ............................................................................ Operations ........................................................................................ 231 232 234 237
11.4.1 Watchdog timer operation .................................................................................................. 237 11.4.2 Interval timer operation ...................................................................................................... 238
CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT ................................................................ 239 12.1 Clock Output Control Circuit Functions .................................................................... 239 12.2 Clock Output Control Circuit Configuration .............................................................. 240
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12.3 Clock Output Function Control Registers ................................................................. 240 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT .............................................................. 243 13.1 Buzzer Output Control Circuit Functions .................................................................. 243 13.2 Buzzer Output Control Circuit Configuration ............................................................ 243 13.3 Buzzer Output Function Control Registers ............................................................... 244 CHAPTER 14 A/D CONVERTER .................................................................................................. 247 14.1 14.2 14.3 14.4 A/D A/D A/D A/D Converter Converter Converter Converter Functions .............................................................................................. Configuration ....................................................................................... Control Registers ................................................................................ Operations ............................................................................................ 247 247 251 254
14.4.1 Basic operations of A/D converter ..................................................................................... 254 14.4.2 Input voltage and conversion results ................................................................................ 256 14.4.3 A/D converter operating mode ........................................................................................... 257
14.5 Cautions on A/D Converter .......................................................................................... 259 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78014 Subseries) ............................... 263 15.1 15.2 15.3 15.4 Serial Serial Serial Serial Interface Interface Interface Interface Channel Channel Channel Channel 0 0 0 0 Functions ......................................................................... Configuration ................................................................... Control Registers ............................................................ Operations ....................................................................... 264 267 271 277
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15.4.1 Operation stop mode .......................................................................................................... 277 15.4.2 3-wire serial I/O mode operation ....................................................................................... 278 15.4.3 SBI mode operation ........................................................................................................... 283 15.4.4 2-wire serial I/O mode operation ....................................................................................... 310 15.4.5 SCK0/P27 pin output manipulation ................................................................................... 317
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78014Y Subseries) ............................ 319 16.1 16.2 16.3 16.4 Serial Serial Serial Serial Interface Interface Interface Interface Channel Channel Channel Channel 0 0 0 0 Functions ......................................................................... Configuration ................................................................... Control Registers ............................................................ Operations ....................................................................... 321 325 330 338
16.4.1 Operation stop mode .......................................................................................................... 338 16.4.2 3-wire serial I/O mode operation ....................................................................................... 339 16.4.3 SBI mode operation ........................................................................................................... 344 16.4.4 2-wire serial I/O mode operation ....................................................................................... 372 16.4.5 I2C bus mode operation ..................................................................................................... 378 16.4.6 Cautions on use of I2C bus mode ..................................................................................... 400 16.4.7 Restrictions on use of I2C bus mode ................................................................................ 403 16.4.8 SCK0/SCL/P27 pin output manipulation ........................................................................... 406
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CHAPTER 17 SERIAL INTERFACE CHANNEL 1 ....................................................................... 409 17.1 17.2 17.3 17.4 Serial Serial Serial Serial Interface Interface Interface Interface Channel Channel Channel Channel 1 1 1 1 Functions ......................................................................... Configuration ................................................................... Control Registers ............................................................ Operations ....................................................................... 409 410 413 418
17.4.1 Operation stop mode .......................................................................................................... 418 17.4.2 3-wire serial I/O mode operation ....................................................................................... 419 17.4.3 3-wire serial I/O mode operation with automatic transmit/receive function .................... 422
CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION ............................................. 447 18.1 18.2 18.3 18.4 Interrupt Interrupt Interrupt Interrupt Function Types .............................................................................................. Sources and Configuration .......................................................................... Function Control Registers ......................................................................... Servicing Operations .................................................................................... 447 447 451 459
18.4.1 Non-maskable interrupt request acknowledge operation ................................................. 459 18.4.2 Maskable interrupt request acknowledge operation ......................................................... 462 18.4.3 Software interrupt request acknowledge operation .......................................................... 465 18.4.4 Multiple interrupt servicing ................................................................................................. 465 18.4.5 Interrupt request reserve ................................................................................................... 468
18.5 Test Function ................................................................................................................. 469
18.5.1 Test function control registers ........................................................................................... 469 18.5.2 Test input signal acknowledge operation .......................................................................... 471
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CHAPTER 19 EXTERNAL DEVICE EXPANSION FUNCTION ................................................... 473 19.1 19.2 19.3 19.4 External Device Expansion Functions ....................................................................... External Device Expansion Control Register ............................................................ External Device Expansion Function Timing ............................................................ Example of Memory Connection ................................................................................. 473 476 477 482
CHAPTER 20 STANDBY FUNCTION ........................................................................................... 483 20.1 Standby Function and Configuration ......................................................................... 483
20.1.1 Standby function ................................................................................................................. 483 20.1.2 Standby function control register ....................................................................................... 484
20.2 Standby Function Operations ...................................................................................... 485
20.2.1 HALT mode ......................................................................................................................... 485 20.2.2 STOP mode ........................................................................................................................ 488
CHAPTER 21 RESET FUNCTION ................................................................................................ 491 21.1 Reset Function ............................................................................................................... 491 CHAPTER 22 PD78P014, 78P014Y ........................................................................................... 495 22.1 Internal Memory Size Switching Register .................................................................. 495
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22.2 PROM Programming ...................................................................................................... 497
22.2.1 Operating modes ................................................................................................................ 497 22.2.2 PROM write procedure ....................................................................................................... 498 22.2.3 PROM read procedure ....................................................................................................... 500
22.3 Erasure Characteristics (for PD78P014DW, 78P014YDW) ..................................... 501 22.4 Opaque Film on Erasure Window (for PD78P014DW, 78P014YDW) .................... 501 22.5 Screening of One-Time PROM Versions .................................................................... 501 CHAPTER 23 INSTRUCTION SET ............................................................................................... 503 23.1 Legend ............................................................................................................................. 504
23.1.1 Operand identifiers and description methods ................................................................... 504 23.1.2 Description of "operation" column ..................................................................................... 505 23.1.3 Description of "flag operation" column .............................................................................. 505
23.2 Operation List ................................................................................................................. 506 23.3 Instructions Listed by Addressing Type .................................................................... 516 APPENDIX A DIFFERENCES BETWEEN PD78014, 78014H, AND 78018F SUBSERIES ..................................................................................... 521 APPENDIX B DEVELOPMENT TOOLS ....................................................................................... 523 B.1 B.2
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Language Processing Software ................................................................................... 525 PROM Programming Tools ........................................................................................... 526
B.2.1 B.2.2 Hardware ............................................................................................................................ 526 Software .............................................................................................................................. 526 Hardware ............................................................................................................................ 527 Software .............................................................................................................................. 528
B.3
Debugging Tools ............................................................................................................ 527
B.3.1 B.3.2
B.4 B.5
OS for IBM PC ................................................................................................................ 531 System-up Method from Other In-Circuit Emulator to In-Circuit Emulator for the 78K/0 series ....................................................................................................... 532
APPENDIX C EMBEDDED SOFTWARE ...................................................................................... 535 C.1 C.2 Real-time OS ................................................................................................................... 536 Fuzzy Inference Development Support System ........................................................ 538
APPENDIX D REGISTER INDEX ................................................................................................. 539 D.1 D.2 Register Index (In Alphabetical Order with Respect to the Register Name) ........ 539 Register Index (In Alphabetical Order with Respect to the Register Symbol) ..... 541
APPENDIX E REVISION HISTORY .............................................................................................. 543
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LIST OF FIGURES (1/7)
Figure No. Title, Page
3-1 4-1 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15
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Pin Input/Output Circuit List .............................................................................................................. Pin Input/Output Circuit List .............................................................................................................. Memory Map (PD78011B, 78011BY) ............................................................................................. Memory Map (PD78012B, 78012BY) ............................................................................................. Memory Map (PD78013, 78013Y) .................................................................................................. Memory Map (PD78014, 78014Y) .................................................................................................. Memory Map (PD78P014, 78P014Y) .............................................................................................
76 92 95 96 97 98 99
Program Counter Configuration ........................................................................................................ 102 Program Status Word Configuration ................................................................................................. 102 Stack Pointer Configuration .............................................................................................................. 104 Data to be Saved to Stack Memory .................................................................................................. 105 Data to be Reset from Stack Memory ............................................................................................... 105 General Register Configuration ........................................................................................................ 107 Data Memory Addressing (PD78011B, 78011BY) .......................................................................... 115 Data Memory Addressing (PD78012B, 78012BY) .......................................................................... 116 Data Memory Addressing (PD78013, 78013Y) .............................................................................. 117 Data Memory Addressing (PD78014, 78014Y) .............................................................................. 118 Data Memory Addressing (PD78P014, 78P014Y) .......................................................................... 119 Port Types ......................................................................................................................................... 129 P00 Block Diagram ........................................................................................................................... 134 P01 to P03 Block Diagrams .............................................................................................................. 135 P04 Block Diagram ........................................................................................................................... 135 P10 to P17 Block Diagrams .............................................................................................................. 136 P20, P21, P23 to P26 Block Diagrams (PD78014 Subseries) ........................................................ 137 P22 and P27 Block Diagrams (PD78014 Subseries) ..................................................................... 138 P20, P21, P23 to P26 Block Diagrams (PD78014Y Subseries) ..................................................... 139 P22 and P27 Block Diagrams (PD78014Y Subseries) ................................................................... 140 P30 to P37 Block Diagrams .............................................................................................................. 141 P40 to P47 Block Diagrams .............................................................................................................. 142 Block Diagram of Falling Edge Detector ........................................................................................... 142 P50 to P57 Block Diagrams .............................................................................................................. 143 P60 to P63 Block Diagrams .............................................................................................................. 145 P64 to P67 Block Diagrams .............................................................................................................. 145 Port Mode Register Format ............................................................................................................... 148 Pull-Up Resistor Option Register Format .......................................................................................... 149 Memory Expansion Mode Register Format ...................................................................................... 150 Key Return Mode Register Format ................................................................................................... 151 Clock Generator Block Diagram ....................................................................................................... 156 Feedback Resistor of Subsystem Clock ........................................................................................... 157 Processor Clock Control Register Format ........................................................................................ 158
5-16 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 6-19 7-1 7-2 7-3
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LIST OF FIGURES (2/7)
Figure No. Title, Page
7-4 7-5 7-6 7-7 7-8 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13
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External Circuit of Main System Clock Oscillator .............................................................................. 160 External Circuit of Subsystem Clock Oscillator ................................................................................. 160 Examples of Resonator with Bad Connection ................................................................................... 161 Main System Clock Stop Function .................................................................................................... 165 System Clock and CPU Clock Switching .......................................................................................... 169 16-Bit Timer/Event Counter (Timer Mode) Block Diagram ............................................................... 174 16-Bit Timer/Event Counter (PWM Mode) Block Diagram ................................................................ 175 16-Bit Timer/Event Counter Output Control Circuit Block Diagram .................................................. 176 Timer Clock Select Register 0 Format .............................................................................................. 179 16-Bit Timer Mode Control Register Format ..................................................................................... 181 16-Bit Timer Output Control Register Format ................................................................................... 182 Port Mode Register 3 Format ............................................................................................................ 183 External Interrupt Mode Register Format .......................................................................................... 184 Sampling Clock Select Register Format ........................................................................................... 185 Interval Timer Configuration Diagram ............................................................................................... 186 Interval Timer Operation Timings ...................................................................................................... 187 Example of D/A Converter Configuration with PWM Output ............................................................. 189 TV Tuner Application Circuit Example .............................................................................................. 189 Configuration Diagram for Pulse Width Measurement by Free-Running Counter ............................ 190 Timing of Pulse Width Measurement Operation by Free-Running Counter (with Both Edges Specified) .............................................................................................................. 191 Timing of Pulse Width Measurement Operation by Means of Restart (with Both Edges Specified) .............................................................................................................. 192 External Event Counter Configuration Diagram ................................................................................ 193 External Event Counter Operation Timings (with Rising Edge Specified) ........................................ 194 Square-Wave Output Operation Timings .......................................................................................... 195 16-Bit Timer Register Start Timings .................................................................................................. 196 Timings after Change of Compare Register during Timer Count Operation ..................................... 196 Capture Register Data Retention Timings ........................................................................................ 197 OVF0 Flag Operation Timing ............................................................................................................ 198 8-Bit Timer/Event Counter Block Diagram ........................................................................................ 205 8-Bit Timer/Event Counter Output Control Circuit 1 Block Diagram ................................................. 206 8-Bit Timer/Event Counter Output Control Circuit 2 Block Diagram ................................................. 206 Timer Clock Select Register 1 Format .............................................................................................. 208 8-Bit Timer Mode Control Register Format ....................................................................................... 209 8-Bit Timer Output Control Register Format ..................................................................................... 210 Port Mode Register 3 Format ............................................................................................................ 211 Interval Timer Operation Timings ...................................................................................................... 212 External Event Counter Operation Timings (with Rising Edge Specified) ........................................ 214 Square-Wave Output Operation Timings .......................................................................................... 215 Interval Timer Operation Timings ...................................................................................................... 216 External Event Counter Operation Timings (with Rising Edge Specified) ........................................ 218
8-14 8-15 8-16 8-17 8-18 8-19 8-20 8-21 8-22 8-23 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12
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LIST OF FIGURES (3/7)
Figure No. Title, Page
9-13 9-14 9-15 9-16 10-1 10-2 10-3 11-1 11-2 11-3 12-1 12-2 12-3 12-4 13-1
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Square-Wave Output Operation Timings .......................................................................................... 219 8-Bit Timer Register Start Timings .................................................................................................... 220 External Event Counter Operation Timings ...................................................................................... 220 Timings after Compare Register Change during Timer Count Operation ......................................... 221 Watch Timer Block Diagram ............................................................................................................. 225 Timer Clock Select Register 2 Format .............................................................................................. 226 Watch Timer Mode Control Register Format .................................................................................... 227 Watchdog Timer Block Diagram ....................................................................................................... 233 Timer Clock Select Register 2 Format .............................................................................................. 235 Watchdog Timer Mode Register Format ........................................................................................... 236 Remote Controlled Output Application Example ............................................................................... 239 Clock Output Control Circuit Block Diagram ..................................................................................... 240 Timer Clock Select Register 0 Format .............................................................................................. 241 Port Mode Register 3 Format ............................................................................................................ 242 Buzzer Output Control Circuit Block Diagram ................................................................................... 243 Timer Clock Select Register 2 Format .............................................................................................. 245 Port Mode Register 3 Format ............................................................................................................ 246 A/D Converter Block Diagram ........................................................................................................... 248 A/D Converter Mode Register Format .............................................................................................. 252 A/D Converter Input Select Register Format .................................................................................... 253 A/D Converter Basic Operation ......................................................................................................... 255 Relationship between Analog Input Voltage and A/D Conversion Result ......................................... 256 A/D Conversion by Hardware Start ................................................................................................... 257 A/D Conversion by Software Start .................................................................................................... 258 Example of Method of Reducing Power Dissipation in Standby Mode ............................................. 259 Analog Input Pin Disposition ............................................................................................................. 260
13-2 13-3 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9
14-10 A/D Conversion End Interrupt Request Generation Timing .............................................................. 261 14-11 AVDD Pin Connection ........................................................................................................................ 261 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 15-9 Serial Bus Interface (SBI) System Configuration Example ............................................................... 265 Serial Bus Configuration Example with 2-Wire Serial I/O ................................................................. 266 Serial Interface Channel 0 Block Diagram ........................................................................................ 268 Timer Clock Select Register 3 Format .............................................................................................. 272 Serial Operating Mode Register 0 Format ........................................................................................ 273 Serial Bus Interface Control Register Format ................................................................................... 274 Interrupt Timing Specification Register Format ................................................................................. 276 3-Wire Serial I/O Mode Timings ........................................................................................................ 281 RELT and CMDT Operations ............................................................................................................ 282
15-10 Circuit of Switching in Transfer Bit Order .......................................................................................... 282
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LIST OF FIGURES (4/7)
Figure No. Title, Page
15-11 Example of Serial Bus Configuration with SBI .................................................................................. 284 15-12 SBI Transfer Timings ........................................................................................................................ 286 15-13 Bus Release Signal ........................................................................................................................... 287 15-14 Command Signal .............................................................................................................................. 287 15-15 Address ............................................................................................................................................. 288 15-16 Slave Selection with Address ............................................................................................................ 288 15-17 Command ......................................................................................................................................... 289 15-18 Data .................................................................................................................................................. 289 15-19 Acknowledge Signal .......................................................................................................................... 290 15-20 Busy Signal and Ready Signal .......................................................................................................... 291 15-21 RELT, CMDT, RELD and CMDD Operations (Master) ..................................................................... 296 15-22 RELD and CMDD Operations (Slave) ............................................................................................... 296 15-23 ACKT Operation ................................................................................................................................ 297 15-24 ACKE Operations .............................................................................................................................. 298 15-25 ACKD Operations ............................................................................................................................. 299 15-26 BSYE Operation ................................................................................................................................ 299 15-27 Pin Configuration .............................................................................................................................. 302 15-28 Address Transmission from Master Device to Slave Device (WUP = 1) .......................................... 305 15-29 Command Transmission from Master Device to Slave Device ......................................................... 306
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15-30 Data Transmission from Master Device to Slave Device .................................................................. 307 15-31 Data Transmission from Slave Device to Master Device .................................................................. 308 15-32 Example of Serial Bus Configuration with 2-Wire Serial I/O ............................................................. 310 15-33 2-Wire Serial I/O Mode Timings ........................................................................................................ 315 15-34 RELT and CMDT Operations ............................................................................................................ 316 15-35 SCK0/P27 Pin Configuration ............................................................................................................. 317 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 Serial Bus Interface (SBI) System Configuration Example ............................................................... 322 Serial Bus Configuration Example with 2-Wire Serial I/O ................................................................. 323 Serial Bus Configuration Example Using I2C Bus ............................................................................ 324 Serial Interface Channel 0 Block Diagram ........................................................................................ 326 Timer Clock Select Register 3 Format .............................................................................................. 331 Serial Operating Mode Register 0 Format ........................................................................................ 332 Serial Bus Interface Control Register Format ................................................................................... 334 Interrupt Timing Specification Register Format ................................................................................. 336 3-Wire Serial I/O Mode Timings ........................................................................................................ 342
16-10 RELT and CMDT Operations ............................................................................................................ 343 16-11 Circuit of Switching in Transfer Bit Order .......................................................................................... 343 16-12 Example of Serial Bus Configuration with SBI .................................................................................. 345 16-13 SBI Transfer Timings ........................................................................................................................ 347 16-14 Bus Release Signal ........................................................................................................................... 348 16-15 Command Signal .............................................................................................................................. 348 16-16 Address ............................................................................................................................................. 349 16-17 Slave Selection with Address ............................................................................................................ 349 16-18 Command ......................................................................................................................................... 350
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LIST OF FIGURES (5/7)
Figure No. Title, Page
16-19 Data .................................................................................................................................................. 350 16-20 Acknowledge Signal .......................................................................................................................... 351 16-21 Busy Signal, Ready Signal ................................................................................................................ 352 16-22 RELT, CMDT, RELD and CMDD Operations (Master) ..................................................................... 357 16-23 RELD and CMDD Operations (Slave) ............................................................................................... 357 16-24 ACKT Operation ................................................................................................................................ 358 16-25 ACKE Operations .............................................................................................................................. 359 16-26 ACKD Operations ............................................................................................................................. 360 16-27 BSYE Operation ................................................................................................................................ 360 16-28 Pin Configuration .............................................................................................................................. 363 16-29 Address Transmission from Master Device to Slave Device (WUP = 1) .......................................... 366 16-30 Command Transmission from Master Device to Slave Device ......................................................... 367 16-31 Data Transmission from Master Device to Slave Device .................................................................. 368 16-32 Data Transmission from Slave Device to Master Device .................................................................. 369 16-33 Example of Serial Bus Configuration with 2-Wire Serial I/O ............................................................. 372 16-34 2-Wire Serial I/O Mode Timings ........................................................................................................ 376 16-35 RELT and CMDT Operations ............................................................................................................ 377 16-36 Serial Bus Configuration Example Using I2C Bus ............................................................................ 378 16-37 I2C Bus Serial Data Transfer Timing ................................................................................................ 379
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16-38 Start Condition .................................................................................................................................. 380 16-39 Address ............................................................................................................................................. 381 16-40 Transfer Direction Specification ........................................................................................................ 381 16-41 Acknowledge Signal .......................................................................................................................... 382 16-42 Stop Condition .................................................................................................................................. 382 16-43 Wait Signal ........................................................................................................................................ 383 16-44 Pin Configuration .............................................................................................................................. 391 16-45 Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait) .............. 393 16-46 Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait) .............. 396 16-47 Start Condition Output ...................................................................................................................... 400 16-48 Slave Wait Release (Transmission) .................................................................................................. 401 16-49 Slave Wait Release (Reception) ....................................................................................................... 402 16-50 SCK0/SCL/P27 Pin Configuration ..................................................................................................... 406 16-51 SCK0/SCL/P27 Pin Configuration ..................................................................................................... 407 16-52 SCL Signal Logic .............................................................................................................................. 407 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 Serial Interface Channel 1 Block Diagram ........................................................................................ 411 Timer Clock Select Register 3 Format .............................................................................................. 414 Serial Operating Mode Register 1 Format ........................................................................................ 415 Automatic Data Transmit/Receive Control Register Format ............................................................. 417 3-Wire Serial I/O Mode Timings ........................................................................................................ 420 Circuit of Switching in Transfer Bit Order .......................................................................................... 421 Basic Transmit/Receive Mode Operation Timings ............................................................................ 426 Basic Transmit/Receive Mode Flowchart .......................................................................................... 427 Buffer RAM Operation in 6-Byte Transmission/Reception (in Basic Transmit/Receive Mode) ......... 428
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LIST OF FIGURES (6/7)
Figure No. Title, Page
17-10 Basic Transmit Mode Operation Timings .......................................................................................... 430 17-11 Basic Transmit Mode Flowchart ........................................................................................................ 431 17-12 Buffer RAM Operation in 6-Byte Transmission (in Basic Transmit Mode) ........................................ 432 17-13 Repeat Transmit Mode Operation Timings ....................................................................................... 434 17-14 Repeat Transmit Mode Flowchart ..................................................................................................... 435 17-15 Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmit Mode) ..................................... 436 17-16 Automatic Transmission/Reception Suspension and Restart ........................................................... 438 17-17 System Configuration when Busy Control Option Is Used ................................................................ 439 17-18 Operation Timings when Using Busy Control Option (BUSY0 = 0) .................................................. 440 17-19 Busy Signal and Wait Release (when BUSY0 = 0) ........................................................................... 440 17-20 Operation Timings when Using Busy & Strobe Control Option (BUSY0 = 0) ................................... 441 17-21 Operation Timing of Bit Shift Detection Function by Busy Signal (when BUSY0 = 1) ...................... 442 17-22 Automatic Data Transmit/Receive Interval ........................................................................................ 443 17-23 Operating Timing in Operating Automatic Transmission/Reception with Internal Clock ................... 444 18-1 18-2 18-3 18-4
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Basic Configuration of Interrupt Function .......................................................................................... 449 Interrupt Request Flag Register Format ........................................................................................... 452 Interrupt Mask Flag Register Format ................................................................................................ 453 Priority Specify Flag Register Format ............................................................................................... 454 External Interrupt Mode Register Format .......................................................................................... 455 Sampling Clock Select Register Format ........................................................................................... 456 Noise Eliminator Input/Output Timing (when rising edge is detected) .............................................. 457 Program Status Word Configuration ................................................................................................. 458 Flowchart from Non-Maskable Interrupt Request Generation to Acknowledge ................................ 460
18-5 18-6 18-7 18-8 18-9
18-10 Non-Maskable Interrupt Request Acknowledge Timing .................................................................... 460 18-11 Non-Maskable Interrupt Request Acknowledge Operation ............................................................... 461 18-12 Interrupt Request Acknowledge Processing Algorithm ..................................................................... 463 18-13 Interrupt Request Acknowledge Timing (Minimum Time) ................................................................. 464 18-14 Interrupt Request Acknowledge Timing (Maximum Time) ................................................................ 464 18-15 Multiple Interrupt Examples .............................................................................................................. 466 18-16 Interrupt Request Reserve ................................................................................................................ 468 18-17 Basic Configuration of Test Function ................................................................................................ 469 18-18 Interrupt Request Flag Register 0H Format ...................................................................................... 470 18-19 Interrupt Mask Flag Register 0H Format ........................................................................................... 470 18-20 Key Return Mode Register Format ................................................................................................... 471 19-1 19-2 19-3 19-4 19-5 19-6 19-7 Memory Map when Using External Device Expansion Function ...................................................... 474 Memory Expansion Mode Register Format ...................................................................................... 476 Instruction Fetch from External Memory ........................................................................................... 478 External Memory Read Timing ......................................................................................................... 479 External Memory Write Timing .......................................................................................................... 480 External Memory Read Modify Write Timing .................................................................................... 481 Example of Memory Connection with PD78014 ............................................................................. 482
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LIST OF FIGURES (7/7)
Figure No. Title, Page
20-1 20-2 20-3 20-4 20-5 21-1 21-2 21-3 21-4 22-1 22-2 22-3 22-4 B-1 B-2 B-3
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Oscillation Stabilization Time Select Register Format ...................................................................... 484 HALT Mode Clear upon Interrupt Request Generation ..................................................................... 486 HALT Mode Clear upon RESET Input .............................................................................................. 487 STOP Mode Clear upon Interrupt Request Generation .................................................................... 489 STOP Mode Clear upon RESET Input .............................................................................................. 490 Block Diagram of Reset Function ..................................................................................................... 491 Timing of Reset by RESET Input ...................................................................................................... 492 Timing of Reset due to Watchdog Timer Overflow ........................................................................... 492 Timing of Reset in STOP Mode by RESET Input ............................................................................. 492 Internal Memory Size Switching Register Format ............................................................................. 496 PROM Write/Verify Timing ................................................................................................................ 498 Write Procedure Flowchart ............................................................................................................... 499 PROM Read Timing .......................................................................................................................... 500 Development Tools Configuration ..................................................................................................... 524 EV-9200GC-64 Package Drawing (for reference only) ..................................................................... 533 EV-9200GC-64 Footprint (for reference only) ................................................................................... 534
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LIST OF TABLES (1/3)
Table No. Title, Page
1-1 1-2 2-1 3-1 4-1 5-1 5-2 5-3 5-4 5-5 6-1 6-2 6-3
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Differences among PD78011B, 78012B, 78013, 78014 and PD78011B(A), 78012B(A), 78013(A), 78014(A) .......................................................................................................................... Mask Options in Mask ROM Versions .............................................................................................. Mask Options in Mask ROM Versions .............................................................................................. Pin Input/Output Circuit Types .......................................................................................................... Pin Input/Output Circuit Types .......................................................................................................... 47 48 61 74 90
Internal ROM Capacity ...................................................................................................................... 100 Vector Table ...................................................................................................................................... 100 Internal High-Speed RAM Capacities ............................................................................................... 101 Absolute Address Corresponding to General Registers ................................................................... 106 Special Function Register List .......................................................................................................... 109 Port Functions (PD78014 Subseries) ............................................................................................. 130 Port Functions (PD78014Y Subseries) ........................................................................................... 132 Port Block Diagram ........................................................................................................................... 134 Pull-Up Resistors for Port 6 .............................................................................................................. 144 Port Mode Register and Output Latch Setting when Alternate Function is Used ............................. 147 Clock Generator Configuration ......................................................................................................... 155 Relationship between CPU Clock and Minimum Instruction Execution Time ................................... 159 Maximum Time Required for CPU Clock Switchover ....................................................................... 168 Timer/Event Counter Operation ........................................................................................................ 172 16-Bit Timer/Event Counter Interval Times ....................................................................................... 172 16-Bit Timer/Event Counter Square-Wave Output Ranges .............................................................. 173 16-Bit Timer/Event Counter Configuration ........................................................................................ 173 16-Bit Timer/Event Counter Interval Times ....................................................................................... 187 16-Bit Timer/Event Counter Square-Wave Output Ranges .............................................................. 195 8-Bit Timer/Event Counter Interval Times ......................................................................................... 200 8-Bit Timer/Event Counter Square-Wave Output Ranges ................................................................ 201 Interval Times when 8-Bit Timer/Event Counters are Used as 16-Bit Timer/Event Counter ............ 202 Square-Wave Output Ranges when 8-Bit Timer/Event Counters are Used as 16-Bit Timer/Event Counter .......................................................................................................... 203 8-Bit Timer/Event Counter Configuration .......................................................................................... 204 8-Bit Timer/Event Counter 1 Interval Times ...................................................................................... 213 8-Bit Timer/Event Counter 2 Interval Times ...................................................................................... 213 8-Bit Timer/Event Counter Square-Wave Output Ranges ................................................................ 215 Interval Times when 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2) are Used as 16-Bit Timer/Event Counter .......................................................................................... 217
6-4 6-5 7-1 7-2 7-3 8-1 8-2 8-3 8-4 8-5 8-6 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9
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LIST OF TABLES (2/3)
Table No. Title, Page
9-10
Square-Wave Output Ranges when 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2) are Used as 16-Bit Tmer/Event Counter ........................................................................................... 219
10-1 10-2 10-3 11-1 11-2 11-3 11-4 11-5 12-1 13-1 14-1 15-1 15-2 15-3 15-4 16-1 16-2 16-3 16-4 16-5 16-6 17-1 17-2 17-3 18-1 18-2 18-3 18-4 18-5 18-6 19-1 19-2
Interval Timer Interval Time .............................................................................................................. 223 Watch Timer Configuration ............................................................................................................... 224 Interval Timer Interval Time .............................................................................................................. 229 Watchdog Timer Inadvertent Program Loop Detection Time ............................................................ 231 Interval Time ..................................................................................................................................... 231 Watchdog Timer Configuration ......................................................................................................... 232 Watchdog Timer Inadvertent Program Loop Detection Time ............................................................ 237 Interval Timer Interval Time .............................................................................................................. 238 Clock Output Control Circuit Configuration ....................................................................................... 240 Buzzer Output Control Circuit Configuration ..................................................................................... 243 A/D Converter Configuration ............................................................................................................. 247 Differences between Channels 0 and 1 ............................................................................................ 263 Difference of Serial Interface Channel 0 Modes ............................................................................... 263 Serial Interface Channel 0 Configuration .......................................................................................... 267 Various Signals in SBI Mode ............................................................................................................ 300 Differences between Channels 0 and 1 ............................................................................................ 319 Difference of Serial Interface Channel 0 Mode ................................................................................. 320 Serial Interface Channel 0 Configuration .......................................................................................... 325 Serial Interface Channel 0 Interrupt Request Signal Generation ...................................................... 329 Various Signals in SBI Mode ............................................................................................................ 361 Signals in the I2C Bus Mode ............................................................................................................. 390 Serial Interface Channel 1 Configuration .......................................................................................... 410 Interval by CPU Processing (in Internal Clock Operation) ................................................................ 444 Interval by CPU Processing (in External Clock Operation) ............................................................... 445 Interrupt Source List .......................................................................................................................... 448 Various Flags Corresponding to Interrupt Request Sources ............................................................ 451 Times from Maskable Interrupt Request Generation to Interrupt Service ......................................... 462 Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing ...................................... 465 Test Input Source .............................................................................................................................. 469 Various Flags Corresponding to Test Input Signal ........................................................................... 470 Pin Functions in External Memory Expansion Mode ........................................................................ 473 State of Port 4 to Port 6 Pins in External Memory Expansion Mode ................................................. 473
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LIST OF TABLES (3/3)
Table No. Title, Page
20-1 20-2 20-3 20-4 21-1 22-1 22-2 22-3 23-1 A-1 B-1 B-2
HALT Mode Operating Status ........................................................................................................... 485 Operation after HALT Mode Clear .................................................................................................... 487 STOP Mode Operating Status .......................................................................................................... 488 Operation after STOP Mode Clear .................................................................................................... 490 Hardware Status after Reset ............................................................................................................. 493 Differences between PD78P014, 78P014Y, and Mask ROM Version ............................................ 495 Internal Memory Size Switching Register Value at Reset ................................................................. 496 PROM Programming Operating Modes ............................................................................................ 497 Operand Identifiers and Description Methods ................................................................................... 504 Major Differences between PD78014, 78014H, and 78018F Subseries ........................................ 521 System-up Method from Other In-Circuit Emulator to IE-78000-R ................................................... 532 System-up Method from Other In-Circuit Emulator to IE-78000-R-A ................................................ 532
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[MEMO]
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OUTLINE (PD78014 Subseries)
CHAPTER 1
OUTLINE (PD78014 Subseries)
1.1 Features * On-chip large-capacity ROM and RAM
Item Part Number Program Memory (ROM) Data Memory Internal high-speed RAM Buffer RAM
PD78011B PD78012B PD78013 PD78014 PD78P014
8 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes 32 KbytesNote 1
512 bytes
32 bytes
1024 bytes 1024 bytesNote 2
Notes 1. 8, 16, 24, or 32 Kbytes can be selected with the memory size switching register (IMS). 2. 512 or 1024 bytes can be selected with IMS.
* External memory expanded space: 64 Kbytes * Minimum instruction execution time changeable from high speed (0.4 s:
to ultra-low speed (122 s: @ 32.768 KHz with subsystem clock) * Bit manipulation can be enabled in all the address space
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@ 10.0 MHz with main system clock)
* Instruction set suitable for system control
* Multiplication/division instruction
* 53 I/O ports (N-ch open-drain: 4) * 8-bit resolution A/D converter: 8 channels
* Low-voltage operation (AVDD = 2.7 to 6.0 V: operable at the same voltage range as CPU)
* Serial interface: * Timer:
2 channels
* 3-wire serial I/O, SBI, 2-wire serial I/O mode: 1 channel * 3-wire serial I/O mode (Automatic transmit/receive function): 1 channel 5 channels : 2 channels : 1 channel : 1 channel * 16-bit timer/event counter : 1 channel * 8-bit timer/event counter * Watch timer * Watchdog timer
* 14 vectored interrupt sources * 2 test inputs * 2 types of on-chip clock oscillator (main system clock and subsystem clock) * Power supply voltage: 2.7 to 6.0 V
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1.2 Application Fields For the PD78011B, 78012B, 78013, 78014, and 78P014 Telephone, VCR, audio system, camera, home electric appliances, etc. For the PD78011B(A), 78012B(A), 78013(A), and 78014(A) Automobile electronic equipment, gas detection breaker, safety equipment, etc. 1.3 Ordering Information Part Number Package 64-pin plastic shrink DIP (750 mils) 64-pin plastic QFP (14 x 14 mm) 64-pin plastic shrink DIP (750 mils) 64-pin plastic QFP (14 x 14 mm) 64-pin plastic shrink DIP (750 mils) 64-pin plastic QFP (14 x 14 mm) 64-pin plastic shrink DIP (750 mils) 64-pin plastic QFP (14 x 14 mm) 64-pin plastic shrink DIP (750 mils) 64-pin ceramic shrink DIP with window (750 mils) 64-pin plastic QFP (14 x 14 mm) 64-pin plastic shrink DIP (750 mils) 64-pin plastic QFP (14 x 14 mm) 64-pin plastic shrink DIP (750 mils) 64-pin plastic QFP (14 x 14 mm) 64-pin plastic shrink DIP (750 mils) 64-pin plastic QFP (14 x 14 mm) 64-pin plastic shrink DIP (750 mils) 64-pin plastic QFP (14 x 14 mm) Internal ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM One-time PROM EPROM One-time PROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM
PD78011BCW-xxx PD78011BGC-xxx-AB8 PD78012BCW-xxx PD78012BGC-xxx-AB8 PD78013CW-xxx PD78013GC-xxx-AB8 PD78014CW-xxx PD78014GC-xxx-AB8 PD78P014CW PD78P014DW PD78P014GC-AB8 PD78011BCW(A)-xxx
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PD78011BGC-xxx-AB8 PD78012BCW(A)-xxx PD78012BGC(A)-xxx-AB8 PD78013CW(A)-xxx PD78013GC(A)-xxx-AB8 PD78014CW(A)-xxx PD78014GC(A)-xxx-AB8
Remark
xxx is ROM code suffix.
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OUTLINE (PD78014 Subseries)
1.4 Quality Grade Part Number Package 64-pin plastic shrink DIP (750 mils) 64-pin plastic QFP (14 x 14 mm) 64-pin plastic shrink DIP (750 mils) 64-pin plastic QFP (14 x 14 mm) 64-pin plastic shrink DIP (750 mils) 64-pin plastic QFP (14 x 14 mm) 64-pin plastic shrink DIP (750 mils) 64-pin plastic QFP (14 x 14 mm) 64-pin plastic shrink DIP (750 mils) 64-pin ceramic shrink DIP with window (750 mils) Quality Grade Standard Standard Standard Standard Standard Standard Standard Standard Standard Not applicable (for function evaluation only) Standard Special Special Special Special Special Special Special Special
PD78011BCW-xxx PD78011BGC-xxx-AB8 PD78012BCW-xxx PD78012BGC-xxx-AB8 PD78013CW-xxx PD78013GC-xxx-AB8 PD78014CW-xxx PD78014GC-xxx-AB8 PD78P014CW PD78P014DW PD78P014GC-AB8 PD78011BCW(A)-xxx PD78011BGC-xxx-AB8 PD78012BCW(A)-xxx PD78012BGC(A)-xxx-AB8 PD78013CW(A)-xxx PD78013GC(A)-xxx-AB8 PD78014CW(A)-xxx PD78014GC(A)-xxx-AB8
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64-pin plastic QFP (14 x 14 mm) 64-pin plastic shrink DIP (750 mils) 64-pin plastic QFP (14 x 14 mm) 64-pin plastic shrink DIP (750 mils) 64-pin plastic QFP (14 x 14 mm) 64-pin plastic shrink DIP (750 mils) 64-pin plastic QFP (14 x 14 mm) 64-pin plastic shrink DIP (750 mils) 64-pin plastic QFP (14 x 14 mm)
Caution
Of the above members, the PD78P014DW should be used only for experiment or function evaluation, because it is not intended for use in equipment that will be mass-produced and require high reliability.
Remark
xxx is the ROM code suffix.
Please refer to the Quality grade on NEC Semiconductor Devices (C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
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1.5 Pin Configurations (Top View) (1) Normal operating mode * 64-pin plastic shrink DIP (750 mils)
PD78011BCW-xxx, 78012BCW-xxx PD78013CW-xxx, 78014CW-xxx, 78P014CW PD78011BCW(A)-xxx, 78012BCW(A)-xxx PD78013CW(A)-xxx, 78014CW(A)-xxx
* 64-pin ceramic shrink DIP with window (750 mils)
PD78P014DW
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P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 VSS P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
AVREF AVDD P17/ANI7 P16/ANI6 P15/ANI5 P14/ANI4 P13/ANI3 P12/ANI2 P11/ANI1 P10/ANI0 AVSS P04/XT1 XT2 IC (VPP) X1 X2 VDD P03/INTP3 P02/INTP2 P01/INTP1 P00/INTP0/TI0 RESET P67/ASTB P66/WAIT P65/WR P64/RD P63 P62 P61 P60 P57/A15 P56/A14
Cautions 1. 2. 3. Remark
Connect IC (Internally Connected) pin directly to VSS. Connect AVDD pin to VDD. Connect AVSS pin to VSS.
Pin connection in parentheses is intended for the PD78P014.
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OUTLINE (PD78014 Subseries)
*
64-pin plastic QFP (14 x 14 mm)
PD78011BGC-xxx-AB8, 78012BGC-xxx-AB8 PD78013GC-xxx-AB8, 78014GC-xxx-AB8, 78P014GC-AB8 PD78011BGC(A)-xxx-AB8, 78012BGC(A)-xxx-AB8 PD78013GC(A)-xxx-AB8, 78014GC(A)-xxx-AB8
P26/SO0/SB1
P25/SI0/SB0
P24/BUSY
P27/SCK0
P22/SCK1
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 VSS
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1 2 3 4 5 6 7 8 9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
P12/ANI2
P21/SO1
P23/STB
P20/SI1
AVREF
AVDD
P11/ANI1 P10/ANI0 AVSS P04/XT1 XT2 IC (VPP) X1 X2 VDD P03/INTP3 P02/INTP2 P01/INTP1 P00/INTP0/TI0 RESET P67/ASTB P66/WAIT
P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6
10 11 12 13 14 15
33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P56/A14
P57/A15
P60
P61
P62
P63
P64/RD
P47/AD7
P52/A10
P53/A11
P54/A12
P55/A13
Cautions 1. 2. 3. Remark
Connect IC (Internally Connected) pin directly to VSS. Connect AVDD pin to VDD. Connect AVSS pin to VSS.
Pin connection in parentheses is intended for the PD78P014.
P65/WR
P50/A8
P51/A9
VSS
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OUTLINE (PD78014 Subseries)
A8 to A15 AD0 to AD7 ANI0 to ANI7 ASTB AVDD AVREF AVSS BUSY BUZ IC P00 to P04 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 Remark
: Address Bus : Address/Data Bus : Analog Input : Address Strobe : Analog Power Supply : Analog Reference Voltage : Analog Ground : Busy : Buzzer Clock : Internally Connected : Port0 : Port1 : Port2 : Port3 : Port4 : Port5 : Port6
PCL RD RESET SB0, SB1 SCK0, SCK1 SI0, SI1 SO0, SO1 STB TI0 to TI2 TO0 to TO2 VDD VPP VSS WAIT WR X1, X2 XT1, XT2
: Programmable Clock : Read Strobe : Reset : Serial Bus : Serial Clock : Serial Input : Serial Output : Strobe : Timer Input : Timer Output : Power Supply : Programming Power Supply : Ground : Wait : Write Strobe : Crystal (Main System Clock) : Crystal (Subsystem Clock)
INTP0 to INTP3 : Interrupt from Peripherals
VPP is intended for the PD78P014. For Mask ROM versions, IC is applied.
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OUTLINE (PD78014 Subseries)
(2) PROM programming mode * * 64-pin plastic shrink DIP (750 mils)
PD78P014CW
64-pin ceramic shrink DIP with window (750 mils)
PD78P014DW
(L)
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D0 D1 D2 D3 D4 D5 D6 D7 VSS A0 A1 A2 A3 A4 A5 A6 A7 A8 (L) A10 A11 A12 A13 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VSS VDD
(L)
VSS (L) Open VPP (L) Open VDD (L) A9 RESET (L) CE OE
(L)
A14
Cautions 1. 2. 3. 4.
(L) VSS RESET Open
: Connect individually to VSS via a pull-down resistor. : Connect to the ground. : Set to the low level. : No connection required.
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OUTLINE (PD78014 Subseries)
*
64-pin plastic QFP (14 x 14 mm)
PD78P014GC-AB8
(L)
D0 D1 D2 D3 D4 D5 D6 D7 VSS A0 A1 A2 A3 A4
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1 2 3 4 5 6 7 8 9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 (L) A9 RESET (L) VSS (L) Open VPP (L) Open VDD (L)
10 11 12 13 14 15
A5 A6
33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
A14
VDD
VSS
(L) OE
A10
A11
A12
A13
VSS
Cautions 1. 2. 3. 4. A0 to A14 CE D0 to D7 OE
(L) VSS RESET Open
: Connect individually to VSS via a pull-down resistor. : Connect to the ground. : Set to the low level. : No connection required. RESET : Reset VDD VPP VSS : Power Supply : Programming Power Supply : Ground
: Address Bus : Chip Enable : Data Bus : Output Enable
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(L)
CE
A7
A8
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OUTLINE (PD78014 Subseries)
1.6 78K/0 Series Expansion The following shows the 78K/0 Series products development. Subseries names are shown inside frames.
Mass-produced products Products under development The subseries whose names end with Y support the I2C bus specifications Control
PD78075BY PD78078Y PD78070AY PD780018AY PD780058 PD780058YNote PD78058F PD78058FY PD78054 PD78054Y PD780034 PD780034Y PD780024 PD780024Y PD78014H PD78018FY PD78018F PD78014 PD78014Y 64-pin PD780001 64-pin PD78002Y PD78002 64-pin 42/44-pin PD78083
100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin
PD78075B PD78078 PD78070A
EMI-noise reduced version of PD78078 A timer was added to the PD78054 and external interface was enhanced ROM-less version of the PD78078 Serial I/O of the PD78078Y was enhanced and the function is limited. Serial I/O of the PD78054 was enhanced and EMI-noise was reduced. EMI-noise reduced version of the PD78054 UART and D/A converter were enhanced to the PD78014 and I/O was enhanced A/D converter of the PD780024 was enhanced Serial I/O of the PD78018F was added and EMI-noise was reduced. EMI-noise reduced version of PD78018F
Low-voltage (1.8 V) operation version of the PD78014, with larger selection of ROM and RAM capacities
An A/D converter and 16-bit timer were added to the PD78002 An A/D converter was added to the PD78002 Basic subseries for control On-chip UART, capable of operating at low voltage (1.8 V)
Inverter control 64-pin 64-pin
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PD780964 PD780924
A/D converter of the PD780924 was enhanced On-chip inverter control circuit and UART. EMI-noise was reduced.
FIPTM drive 100-pin 100-pin 80-pin 80-pin
PD780208 PD780228 PD78044H PD78044F
The I/O and FIP C/D of the PD78044F were enhanced, Display output total: 53 The I/O and FIP C/D of the PD78044H were enhanced, Display output total: 48 An N-ch open drain I/O was added to the PD78044F, Display output total: 34 Basic subseries for driving FIP, Display output total: 34
78K/0 Series
LCD drive 100-pin 100-pin 100-pin
PD780308 PD78064B PD78064 PD780308Y PD78064Y
The SIO of the PD78064 was enhanced, and ROM, RAM capacity increased EMI-noise reduced version of the PD78064 Basic subseries for driving LCDs, On-chip UART
80-pin 80-pin
IEBusTM supported PD78098B
PD78098
EMI-noise reduced version of the PD78098 An IEBus controller was added to the PD78054
80-pin
Meter control PD780973 LV
On-chip automobile meter driving controller/driver
64-pin
PD78P0914
On-chip PWM output, LV digital code decoder, and Hsync counter
Note
Under planning
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OUTLINE (PD78014 Subseries)
The following table shows the differences among subseries functions.
Function Part Number Control PD78075B ROM Capacity 32K to 40K 48K to 60K -- 24K to 60K 2ch 2ch 3ch (time division UART: 1ch) 3ch (UART: 1ch) 61 68 2.7 V 1.8 V Timer 8-bit 16-bit Watch WDT 4ch 1ch 1ch 1ch 8-bit 10-bit 8-bit A/D 8ch A/D -- D/A 2ch 3ch (UART: 1ch) 88 Serial Interface I/O VDD MIN. Value 1.8 V External Expansion
PD78078 PD78070A PD780058 PD78058F PD78054 PD780034 PD780024 PD78014H PD78018F PD78014 PD780001 PD78002 PD78083
Inverter PD780964 control
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48K to 60K 16K to 60K 8K to 32K -- 8ch 8ch -- --
69
2.7 V 2.0 V
3ch (UART: 1ch, time division 3-wire: 1ch) 2ch
51
1.8 V
53
1.8 V
8K to 60K 8K to 32K 8K 8K to 16K -- -- 1ch -- 8K to 32K 3ch Note -- 1ch -- 8ch -- 8ch 32K to 60K 48K to 60K 32K to 48K 16K to 40K 2ch 1ch 1ch 1ch 8ch -- -- 2ch 3ch 2ch 1ch -- 1ch 1ch -- 1ch 2ch 3ch (time division UART: 1ch) 2ch (UART: 1ch) 57 2.0 V -- 1ch 8ch 8ch -- -- -- 2ch 1ch 74 72 68 2.7 V 4.5 V 2.7 V -- -- 1ch (UART: 1ch) 2ch (UART: 2ch) 1ch 39 53 33 47 1.8 V 2.7 V -- 2.7 V --
PD780924 PD780208 PD780228 PD78044H PD78044F
FIP drive
LCD drive
PD780308B 48K to 60K PD78064B PD78064
32K 16K to 32K 40K to 60K 32K to 60K 24K to 32K
IEBus
PD78098B
2ch
1ch
1ch
1ch
8ch
--
2ch
3ch (UART: 1ch)
69
2.7 V
supported PD78098 Meter control LV
PD780973
3ch
1ch
1ch
1ch
5ch
--
--
2ch (UART: 1ch)
56
4.5 V
--
PD78P0914 32K
6ch
--
--
1ch
8ch
--
--
2ch
54
4.5 V
Note 10-bit timer: 1 channel
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OUTLINE (PD78014 Subseries)
1.7 Block Diagram
TO0/P30 TI0/INTP0/P00 TO1/P31 TI1/P33 TO2/P32 TI2/P34
16-bit TIMER/ EVENT COUNTER 8-bit TIMER/ EVENT COUNTER 1 8-bit TIMER/ EVENT COUNTER 2 WATCHDOG TIMER
P00 PORT0 P01 to P03 P04
PORT1
P10 to P17
PORT2
P20 to P27
PORT3
P30 to P37
WATCH TIMER SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 SERIAL INTERFACE 0 78K/0 CPU CORE ROM
PORT4
P40 to P47
PORT5
P50 to P57
PORT6 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 ANI0/P10 to ANI7/P17 AVDD AVSS AVREF
P60 to P67
SERIAL INTERFACE 1 EXTERNAL ACCESS
AD0/P40 to AD7/P47 A8/P50 to A15/P57 RD/P64 WR/P65 WAIT/P66 ASTB/P67 RESET
RAM
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A/D CONVERTER
INTP0/P00 to INTP3/P03 BUZ/P36
INTERRUPT CONTROL BUZZER OUTPUT CLOCK OUTPUT CONTROL
SYSTEM CONTROL
X1 X2 XT1/P04 XT2
PCL/P35
VDD
VSS
IC (Vpp)
Remarks
1. 2.
The internal ROM and RAM capacities depend on the product. Pin connection in parentheses is intended for the PD78P014.
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OUTLINE (PD78014 Subseries)
1.8 Outline of Function
PD78011B
Mask ROM
Part Number Item Internal memory ROM
PD78012B
PD78013
PD78014
PD78P014
One-time PROM/EPROM
8 Kbytes High-speed RAM Buffer RAM Memory space General registers Minimum instruction execution time When main system clock selected When subsystem clock selected 512 bytes 32 bytes 64 Kbytes
16 Kbytes
24 Kbytes 1024 bytes
32 Kbytes
32 KbytesNote 1 1024 bytesNote 2
8 bits x 8 registers x 4 banks 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s (@ 10.0 MHz) 122 s (@ 32.768 kHz) * 16-bit operation * Multiply/divide (8 bits x 8 bits, 16 bits / 8 bits) * Bit manipulation (set, reset, test, and Boolean operation) * BCD adjust, and other related operations
Instruction set
I/O ports
Total * CMOS input * CMOS I/O
: 53 I/O port pins : 2 inputs : 47 inputs/outputs (on-chip pull-up resistor can be turned on/off by software.)
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* N-ch open-drain I/O
: 4 inputs/outputs (15-V withstand, on-chip pull-up resistor with mask options in mask ROM versions only)
A/D converter
* 8-bit resolution x 8 channels * Low-voltage operation: AVDD = 2.7 to 6.0 V * 3-wire serial I/O, SBI, 2-wire serial I/O mode selectable: 1 channel * 3-wire serial I/O mode (Maximum 32-byte on-chip automatic transmit/receive function): 1 channel
Serial interface
Timer
* 16-bit timer/event counter * 8-bit timer/event counter * Watch timer * Watchdog timer
: 1 channel : 2 channels : 1 channel : 1 channel
Notes 1. 8, 16, 24, or 32 Kbytes can be selected by memory size switching register (IMS). 2. 512 or 1024 bytes can be selected by IMS.
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OUTLINE (PD78014 Subseries)
Part Number Item Timer output Clock output
PD78011B
PD78012B
PD78013
PD78014
PD78P014
3 outputs: (14-bit PWM generation possible from one output) 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz (@ 10.0 MHz with main system clock) 32.768 kHz (@ 32.768 kHz with subsystem clock)
Buzzer output Vectored interrupt sources Test input Power supply voltage Operating ambient temperature Package Maskable Non-maskable Software
2.4 kHz, 4.9 kHz, 9.8 kHz (@ 10.0 MHz with main system clock) Internal Internal 1 Internal : 1, external :1 : 8, :1 external :4
VDD = 2.7 to 6.0 V TA = -40 to +85C * 64-pin plastic shrink DIP (750 mils) * 64-pin plastic QFP (14 x 14 mm) * 64-pin ceramic shrink DIP with window (750 mils): PD78P014 only
1.9 Differences among PD78011B, 78012B, 78013, 78014 and PD78011B(A), 78012B(A), 78013(A), 78014(A)
Table 1-1. Differences among PD78011B, 78012B, 78013, 78014 and PD78011B(A), 78012B(A), 78013(A), 78014(A)
Part Number
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PD78011B, 78012B, 78013, 78014
Standard
PD78011B(A), 78012B(A),
78013(A), 78014(A) Special
Item Quality grade
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OUTLINE (PD78014 Subseries)
1.10 Mask Options The mask ROM versions (PD78011B, PD78012B, PD78013, PD78014) have the mask options. By specifying the mask options when ordering, the pull-up resistors and pull-down resistors listed in Table 1-2 can be incorporated. When these resistors are necessary, the number of external components and mounting space can be saved by utilizing the mask options. Mask options provided in the PD78014 Subseries are shown in Table 1-2.
Table 1-2. Mask Options in Mask ROM Versions
Pin Name P60 to P63 Mask Option Pull-down resistors can be incorporated bit-wise.
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CHAPTER 2
OUTLINE (PD78014Y Subseries)
CHAPTER 2
OUTLINE (PD78014Y Subseries)
2.1 Features
* On-chip large-capacity ROM and RAM
Item Part Number Program Memory (ROM) Data Memory Internal high-speed RAM Buffer RAM
PD78011BY PD78012BY PD78013Y PD78014Y PD78P014Y
8 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes 32 KbytesNote 1
512 bytes
32 bytes
1024 bytes 1024 bytesNote 2
Notes 1. 8, 16, 24, or 32 Kbytes can be selected by memory size switching register (IMS). 2. 512 or 1024 bytes can be selected by IMS.
* External memory expanded space: 64 Kbytes * Minimum instruction execution time changeable from high speed (0.4 s:
to ultra-low speed (122 s: @ 32.768 kHz with subsystem clock)
@ 10 MHz with main system clock)
*
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Instruction set suitable for system control * Bit manipulation enable in all the address space * Multiplication/division instruction
* 53 I/O ports (N-ch open-drain: 4) * 8-bit resolution A/D converter: 8 channels
* Low-voltage operation (AVDD = 2.7 to 6.0 V: operable at the same supply voltage range as CPU)
* Serial interface: * Timer:
2 channels
* 3-wire serial I/O, SBI, 2-wire serial I/O, I2C bus mode: 1 channel * 3-wire serial I/O mode (Automatic transmit/receive function): 1 channel 5 channels : 2 channels : 1 channel : 1 channel * 16-bit timer/event counter : 1 channel * 8-bit timer/event counter * Watch timer * Watchdog timer 14 vectored interrupt sources
* * 2 test inputs * 2 types of on-chip clock oscillator (main system clock and subsystem clock) * Power supply voltage: VDD = 2.7 to 6.0 V
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OUTLINE (PD78014Y Subseries)
2.2 Application Fields Telephone, VCR, audio system, camera, home electric appliances, etc. 2.3 Ordering Information Part Number Package 64-pin plastic shrink DIP (750 mils) 64-pin plastic QFP (14 x 14 mm) 64-pin plastic shrink DIP (750 mils) 64-pin plastic QFP (14 x 14 mm) 64-pin plastic shrink DIP (750 mils) 64-pin plastic QFP (14 x 14 mm) 64-pin plastic shrink DIP (750 mils) 64-pin plastic QFP (14 x 14 mm) 64-pin plastic shrink DIP (750 mils) 64-pin ceramic shrink DIP with window (750 mils) 64-pin plastic QFP (14 x 14 mm) Internal ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM One-time PROM EPROM One-time PROM
PD78011BYCW-xxx PD78011BYGC-xxx-AB8 PD78012BCW-xxx PD78012BYGC-xxx-AB8 PD78013YCW-xxx PD78013YGC-xxx-AB8 PD78014YCW-xxx PD78014YGC-xxx-AB8 PD78P014YCW PD78P014YDW PD78P014YGC-AB8
Remark xxx is ROM code suffix. 2.4 Quality Grade Part Number
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Package 64-pin plastic shrink DIP (750 mils) 64-pin plastic QFP (14 x 14 mm) 64-pin plastic shrink DIP (750 mils) 64-pin plastic QFP (14 x 14 mm) 64-pin plastic shrink DIP (750 mils) 64-pin plastic QFP (14 x 14 mm) 64-pin plastic shrink DIP (750 mils) 64-pin plastic QFP (14 x 14 mm) 64-pin plastic shrink DIP (750 mils) 64-pin ceramic shrink DIP with window (750 mils)
Quality Grade Standard Standard Standard Standard Standard Standard Standard Standard Standard Not applicable (for function evaluation only) Standard
PD78011BYCW-xxx PD78011BYGC-xxx-AB8 PD78012BYCW-xxx PD78012BYGC-xxx-AB8 PD78013YCW-xxx PD78013YGC-xxx-AB8 PD78014YCW-xxx PD78014YGC-xxx-AB8 PD78P014YCW PD78P014YDW PD78P014YGC-AB8
Caution
64-pin plastic QFP (14 x 14 mm)
Of the above members, the PD78P014YDW should be used only for experiment or function evaluation, because it is not intended for use in equipment that will be mass-produced and require high reliability.
Remark xxx is the ROM code suffix. Please refer to the Quality grade on NEC Semiconductor Devices (C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
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2.5 Pin Configurations (Top View) (1) Normal operating mode * 64-pin plastic shrink DIP (750 mils)
PD78011BYCW-xxx, 78012BYCW-xxx PD78013YCW-xxx, 78014YCW-xxx, 78P014YCW
* 64-pin ceramic shrink DIP with window (750 mils)
PD78P014YDW
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P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0/SDA0 P26/SO0/SB1/SDA1 P27/SCK0/SCL P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 VSS P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
AVREF AVDD P17/ANI7 P16/ANI6 P15/ANI5 P14/ANI4 P13/ANI3 P12/ANI2 P11/ANI1 P10/ANI0 AVSS P04/XT1 XT2 IC (VPP) X1 X2 VDD P03/INTP3 P02/INTP2 P01/INTP1 P00/INTP0/TI0 RESET P67/ASTB P66/WAIT P65/WR P64/RD P63 P62 P61 P60 P57/A15 P56/A14
Cautions 1. Connect IC (Internally Connected) pin directly to VSS. 2. Connect AVDD pin to VDD. 3. Connect AVSS pin to VSS. Remark Pin connection in parentheses is intended for the PD78P014Y.
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*
64-pin plastic QFP (14 x 14 mm)
PD78011BYGC-xxx-AB8, 78012BYGC-xxx-AB8 PD78013YGC-xxx-AB8, 78014YGC-xxx-AB8, 78P014YGC-AB8
P26/SO0/SB1/SDA1
P25/SI0/SB0/SDA0
P27/SCK0/SCL
P24/BUSY
P22/SCK1
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 VSS P40/AD0
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1 2 3 4 5 6 7 8 9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
P12/ANI2
P21/SO1
P23/STB
P20/SI1
AVREF
AVDD
P11/ANI1 P10/ANI0 AVSS P04/XT1 XT2 IC (VPP) X1 X2 VDD P03/INTP3 P02/INTP2 P01/INTP1 P00/INTP0/TI0 RESET P67/ASTB P66/WAIT
10 11 12 13 14 15
P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6
33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P56/A14
P57/A15
P60
P61
P62
P63
P64/RD
P47/AD7
P52/A10
P53/A11
P54/A12
P55/A13
Cautions 1. Connect IC (Internally Connected) pin directly to VSS. 2. Connect AVDD pin to VDD. 3. Connect AVSS pin to VSS. Remark Pin connection in parentheses is intended for the PD78P014Y.
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P65/WR
P50/A8
P51/A9
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OUTLINE (PD78014Y Subseries)
A8 to A15 AD0 to AD7 ANI0 to ANI7 ASTB AVDD AVREF AVSS BUSY BUZ IC P00 to P04 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 PCL
: Address Bus : Address/Data Bus : Analog Input : Address Strobe : Analog Power Supply : Analog Reference Voltage : Analog Ground : Busy : Buzzer Clock : Internally Connected : Port0 : Port1 : Port2 : Port3 : Port4 : Port5 : Port6 : Programmable Clock
RD RESET SB0, SB1 SCK0, SCK1 SCL SDA0, SDA1 SI0, SI1 SO0, SO1 STB TI0 to TI2 TO0 to TO2 VDD VPP VSS WAIT WR X1, X2 XT1, XT2
: Read Strobe : Reset : Serial Bus : Serial Clock : Serial Clock : Serial Data : Serial Input : Serial Output : Strobe : Timer Input : Timer Output : Power Supply : Programming Power Supply : Ground : Wait : Write Strobe : Crystal (Main System Clock) : Crystal (Subsystem Clock)
INTP0 to INTP3 : Interrupt from Peripherals
Remark VPP is intended for the PD78P014Y. For Mask ROM versions, IC is applied.
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(2) PROM programming mode * * 64-pin plastic shrink DIP (750 mils)
PD78P014YCW
64-pin ceramic shrink DIP with window (750 mils)
PD78P014YDW
(L)
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D0 D1 D2 D3 D4 D5 D6 D7 VSS A0 A1 A2 A3 A4 A5 A6 A7 A8 (L) A10 A11 A12 A13 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VSS VDD
(L)
VSS (L) Open VPP (L) Open VDD (L) A9 RESET (L) CE OE
(L)
A14
Cautions 1. (L) 2. VSS 3. RESET 4. Open
: Connect individually to VSS via a pull-down resistor. : Connect to the ground. : Set to the low level. : No connection required.
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*
64-pin plastic QFP (14 x 14 mm)
PD78P014YGC-AB8
(L) (L)
D0 D1 D2 D3 D4 D5 D6 D7 VSS A0 A1 A2 A3 A4
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1 2 3 4 5 6 7 8 9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 (L) A9 RESET (L) (L) VSS (L) Open VPP (L) Open VDD
10 11 12 13 14 15
A5 A6
33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
A14
VDD
VSS
OE
A10
A11
A12
A13
VSS
Cautions 1. (L) 2. VSS 3. RESET 4. Open A0 to A14 CE D0 to D7 OE
: Connect individually to VSS via a pull-down resistor. : Connect to the ground. : Set to low level. : No connection required. RESET : Reset VDD VPP VSS : Power Supply : Programming Power Supply : Ground
: Address Bus : Chip Enable : Data Bus : Output Enable
(L)
CE
A7
A8
(L)
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2.6 78K/0 Series Expansion The following shows the 78K/0 Series products development. Subseries names are shown inside frames.
Mass-produced products Products under development The subseries whose names end with Y support the I2C bus specifications Control
PD78075BY PD78078Y PD78070AY PD780018AY PD780058 PD780058YNote PD78058F PD78058FY PD78054 PD78054Y PD780034 PD780034Y PD780024 PD780024Y PD78014H PD78018FY PD78018F PD78014 PD78014Y 64-pin PD780001 64-pin PD78002Y PD78002 64-pin 42/44-pin PD78083
100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin
PD78075B PD78078 PD78070A
EMI-noise reduced version of PD78078 A timer was added to the PD78054 and external interface was enhanced ROM-less version of the PD78078 Serial I/O of the PD78078Y was enhanced and the function is limited. Serial I/O of the PD78054 was enhanced and EMI-noise was reduced. EMI-noise reduced version of the PD78054 UART and D/A converter were enhanced to the PD78014 and I/O was enhanced A/D converter of the PD780024 was enhanced Serial I/O of the PD78018F was added and EMI-noise was reduced. EMI-noise reduced version of PD78018F
Low-voltage (1.8 V) operation version of the PD78014, with larger selection of ROM and RAM capacities
An A/D converter and 16-bit timer were added to the PD78002 An A/D converter was added to the PD78002 Basic subseries for control On-chip UART, capable of operating at low voltage (1.8 V)
Inverter control 64-pin 64-pin
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PD780964 PD780924
A/D converter of the PD780924 was enhanced On-chip inverter control circuit and UART. EMI-noise was reduced.
FIPTM drive 100-pin 100-pin 80-pin 80-pin
PD780208 PD780228 PD78044H PD78044F
The I/O and FIP C/D of the PD78044F were enhanced, Display output total: 53 The I/O and FIP C/D of the PD78044H were enhanced, Display output total: 48 An N-ch open drain I/O was added to the PD78044F, Display output total: 34 Basic subseries for driving FIP, Display output total: 34
78K/0 Series
LCD drive 100-pin 100-pin 100-pin
PD780308 PD78064B PD78064 PD780308Y PD78064Y
The SIO of the PD78064 was enhanced, and ROM, RAM capacity increased EMI-noise reduced version of the PD78064 Basic subseries for driving LCDs, On-chip UART
80-pin 80-pin
IEBusTM supported PD78098B
PD78098
EMI-noise reduced version of the PD78098 An IEBus controller was added to the PD78054
80-pin
Meter control PD780973 LV
On-chip automobile meter driving controller/driver
64-pin
PD78P0914
On-chip PWM output, LV digital code decoder, and Hsync counter
Note
Under planning
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The following table shows the differences among Y subseries functions.
Function Part number Control ROM Capacity Configuration of Serial Interface I/O VDD MIN. Value 3-wire/2-wire/I C
2
PD78075BY PD78078Y PD78070AY PD780018AY
32K to 40K 48K to 60K -- 48K to 60K
: 1ch
88
1.8 V
3-wire with automatic transmit/receive function : 1ch 3-wire/UART : 1ch 61 88 2.7 V
3-wire with automatic transmit/receive function : 1ch Time division 3-wire : 1ch I2C bus (supports multi-master) : 1ch
PD780058Y
24K to 60K
3-wire/2-wire/I2C : 1ch 3-wire with automatic transmit/receive function : 1ch 3-wire/time division UART : 1ch 3-wire/2-wire/I2C : 1ch 3-wire with automatic transmit/receive function : 1ch 3-wire/UART : 1ch UART 3-wire I2C bus (supports multi-master) : 1ch : 1ch : 1ch
68
1.8 V
PD78058FY PD78054Y PD780034Y PD780024Y PD78018FY PD78014Y PD78002Y
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48K to 60K 16K to 60K 8K to 32K
69
2.7 V 2.0 V
51
1.8 V
8K to 60K
3-wire/2-wire/I2C : 1ch 3-wire with automatic transmit/receive function : 1ch 3-wire/2-wire/SBI/I2C : 1ch 3-wire with automatic transmit/receive function : 1ch 3-wire/2-wire/SBI/I2C 3-wire/2-wire/I2C 3-wire/time division UART 3-wire 3-wire/2-wire/I2C 3-wire/UART : 1ch : 1ch : 1ch : 1ch : 1ch : 1ch
53
8K to 32K
2.7 V
8K to 16K 48K to 60K
LCD drive
PD780308Y
57
2.0 V
PD78064Y
16K to 32K
Remark The functions except serial interface are common with subseries without Y.
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2.7 Block Diagram
TO0/P30 TI0/INTP0/P00 TO1/P31 TI1/P33 TO2/P32 TI2/P34
16-bit TIMER/ EVENT COUNTER 8-bit TIMER/ EVENT COUNTER 1 8-bit TIMER/ EVENT COUNTER 2 WATCHDOG TIMER
P00 PORT0 P01 to P03 P04
PORT1
P10 to P17
PORT2
P20 to P27
PORT3
P30 to P37
WATCH TIMER SI0/SB0/SDA0/P25 SO0/SB1/SDA1/P26 SCK0/SCL/P27 SERIAL INTERFACE 0 78K/0 CPU CORE ROM
PORT4
P40 to P47
PORT5
P50 to P57
PORT6 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 ANI0/P10 to ANI7/P17 AVDD AVSS AVREF
P60 to P67
SERIAL INTERFACE 1 EXTERNAL ACCESS
AD0/P40 to AD7/P47 A8/P50 to A15/P57 RD/P64 WR/P65 WAIT/P66 ASTB/P67 RESET
RAM
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A/D CONVERTER
INTP0/P00 to INTP3/P03 BUZ/P36
INTERRUPT CONTROL BUZZER OUTPUT CLOCK OUTPUT CONTROL
SYSTEM CONTROL
X1 X2 XT1/P04 XT2
PCL/P35
VDD
VSS
IC (VPP)
Remarks
1. 2.
The internal ROM and RAM capacities depend on the product. Pin connection in parentheses is intended for the PD78P014Y.
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2.8 Outline of Function
Part Number Item Internal memory 8 Kbytes High-speed RAM Buffer RAM Memory space General registers Minimum instruction execution time When main system clock selected When subsystem clock selected * 16-bit operation * Multiply/divide (8 bits x 8 bits, 16 bits / 8 bits) * Bit manipulation (set, reset, test, and Boolean operation) * BCD adjust, and other related operations I/O ports Total * CMOS input * CMOS I/O : 53 I/O ports : 2 inputs : 47 inputs/outputs (on-chip pull-up resistor can be turn on/off by software.) * N-ch open-drain I/O
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PD78011BY
Mask ROM
PD78012BY
PD78013Y
PD78014Y
PD78P014Y
One-time PROM/EPROM
ROM
16 Kbytes
24 Kbytes 1024 bytes
32 Kbytes
32 KbytesNote 1 1024 bytes Note 2
512 bytes 32 bytes 64 Kbytes 8 bits x 8 registers x 4 banks
0.4 s/0.8 s/1.6 s/3.2 s/6.4 s (@ 10.0 MHz) 122 s (@ 32.768 kHz)
Instruction set
: 4 inputs/outputs (15-V withstand, on-chip pull-up resistor with mask options in mask ROM versions only)
A/D converter
* 8-bit resolution x 8 channels * Low-voltage operation: AVDD = 2.7 to 6.0 V * 3-wire serial I/O, SBI, 2-wire serial I/O, I2C bus mode selectable: 1 channel * 3-wire serial I/O mode (Maximum 32-byte on-chip automatic transmit/receive function): 1 channel
Serial interface
Timer
* 16-bit timer/event counter * 8-bit timer/event counter * Watch timer * Watchdog timer
: 1 channel : 2 channels : 1 channel : 1 channel
Notes 1. 8, 16, 24, or 32 Kbytes can be selected by memory size switching register (IMS). 2. 512 or 1024 bytes can be selected by IMS.
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Part Number Item Timer output Clock output
PD78011BY
PD78012BY
PD78013Y
PD78014Y
PD78P014Y
3 outputs: (14-bit PWM generation possible from one output) 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz (@ 10.0 MHz with main system clock) 32.768 kHz (@ 32.768 kHz with subsystem clock)
Buzzer output Vectored interrupt sources Test input Power supply voltage Operating ambient temperature Package Maskable Non-maskable Software
2.4 kHz, 4.9 kHz, 9.8 kHz (@ 10.0 MHz with main system clock) Internal Internal 1 Internal : 1, external :1 : 8, :1 external :4
VDD = 2.7 to 6.0 V TA = -40 to +85C * 64-pin plastic shrink DIP (750 mil) * 64-pin plastic QFP (14 x 14 mm) * 64-pin ceramic shrink DIP with window (750 mils): PD78P014Y only
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OUTLINE (PD78014Y Subseries)
2.9 Mask Options The mask ROM versions (PD78011BY, PD78012BY, PD78013Y, PD78014Y) have mask options. By specifying the mask options when ordering, the pull-up resistors and pull-down resistors listed in Table 2-1 can be incorporated. When these resistors are necessary, the number of external components and mounting space can be saved by utilizing the mask options. Mask options provided in the PD78014Y subseries are shown in Table 2-1.
Table 2-1. Mask Options in Mask ROM Versions
Pin Name P60 to P63 Mask Option Pull-up resistors can be incorporated bit-wise.
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[MEMO]
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PIN FUNCTION (PD78014 Subseries)
3.1 Pin Function List 3.1.1 Normal operating mode pins (1) Port pins (1/2)
Pin Name Input/ Output P00 P01 P02 P03 P04Note 1 P10 to P17 Input Input/ Output Port 1 8-bit input/output port. Input/output specifiable bit-wise. If used as an input port, an on-chip pull-up resistor can be connected by softwareNote 2. P20 P21 P22 P23
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Function
After Reset
Alternate Function INTP0/TI0 INTP1 INTP2 INTP3
Input Input/ Output
Port 0 5-bit input/output port
Input only Input/output specifiable bit-wise. If used as an input port, an on-chip pull-up resistor can be connected by software. Input only
Input Input
Input Input
XT1 ANI0 to ANI7
Input/ Output
Port 2 8-bit input/output port. Input/output specifiable bit-wise. If used as an input port, an on-chip pull-up resistor can be connected by software.
Input
SI1 SO1 SCK1 STB BUSY SI0/SB0 SO0/SB1 SCK0
P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 Input/ Output
Port 3 8-bit input/output port. LED can be driven directly. Input/output specifiable bit-wise. If used as an input port, an on-chip pull-up resistor can be connected by software.
Input
TO0 TO1 TO2 TI1 TI2 PCL BUZ --
Notes 1. When the P04/XT1 pin is used as an input port, set the bit 6 (FRC) of the processor clock control register (PCC) to 1 (do not use the on-chip feedback resistor of the subsystem clock oscillator). 2. When pins P10/ANI0 to P17/ANI7 are used as an analog input of the A/D converter, the on-chip pull-up resistor is automatically disabled.
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(1) Port pins (2/2)
Pin Name Input/ Output P40 to P47 Input/ Output Port 4 8-bit input/output port. Input/output specifiable in 8-bit wise. When used as an input port, an on-chip pull-up resistor can be connected by software. Test input flag (KRIF) is set to 1 by falling edge detection. P50 to P57 Input/ Output Port 5 8-bit input/output port. Input/output specifiable in 8-bit wise. LED can be driven directly. When used as an input port, an on-chip pull-up resistor can be connected by software. P60 P61 P62 P63 P64 P65 P66 P67
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Function
After Reset Input
Alternate Function AD0 to AD7
Input
A8 to A15
Input/ Output
Port 6 8-bit input/output port. Input/output specifiable bit-wise.
N-ch open drain input/output port. On-chip pull-up resistor can be specified by mask option. LED can be driven directly. When used as an input port, an on-chip pull-up resistor can be connected by software.
Input
--
RD WR WAIT ASTB
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(2) Non-Port Pins (1/2)
Pin Name Input/ Output INTP0 INTP1 INTP2 INTP3 SI0 SI1 SO0 SO1 SB0 SB1 SCK0 SCK1 STB BUSY TI0 TI1 TI2 TO0 TO1 TO2
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Function
After Reset
Alternate Function P00/TI0 P01 P02
Input
External interrupt request inputs with specifiable valid edges (rising edge, falling edge, both rising and falling edges).
Input
External interrupt request input with falling edge detection Input Serial interface serial data input
Input Input
P03 P25/SB0 P20
Output
Serial interface serial data output
Input
P26/SB1 P21
Input/ Output Input/ Output Output Input Input
Serial interface serial data input/output
Input
P25/SI0 P26/SO0
Serial interface serial clock input/output
Input
P27 P22
Serial interface automatic transmit/receive strobe output Serial interface automatic transmit/receive busy input External count clock input to 16-bit timer (TM0) External count clock input to 8-bit timer (TM1) External count clock input to 8-bit timer (TM2)
Input Input Input
P23 P24 P00/INTP0 P33 P34
Output
16-bit timer (TM0) output (also used for 14-bit PWM output) 8-bit timer (TM1) output 8-bit timer (TM2) output
Input
P30 P31 P32
PCL BUZ AD0 to AD7
Output Output Input/ Output
Clock output (for main system clock and subsystem clock trimming) Buzzer output Low-order address/data bus at external memory expansion.
Input Input Input
P35 P36 P40 to P47
A8 to A15 RD WR WAIT ASTB
Output Output
High-order address bus at external memory expansion. External memory read operation strobe signal output. External memory write operation strobe signal output.
Input Input
P50 to P57 P64 P65
Input Output
Wait insertion at external memory access. Strobe output which latches the address data output for ports 4 or 5 to access external memory.
Input Input
P66 P67
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(2) Non-Port Pins (2/2)
Pin Name Input/ Output ANI0 to ANI7 AVREF AVDD AVSS RESET X1 X2 XT1 XT2 VDD VPP Input Input -- -- Input Input -- Input -- -- -- Positive power supply High-voltage application for program write/verify. Connect directly to VSS in normal operating mode. VSS IC -- -- Ground potential Internally connected. Connect directly to VSS. -- -- -- -- Crystal connection for subsystem clock oscillation A/D converter analog input. A/D converter reference voltage input. A/D converter analog power supply. Connect to VDD. A/D converter ground potential. Connect to VSS. System reset input Crystal connection for main system clock oscillation Function After Reset Input -- -- -- -- -- -- Input -- -- -- Alternate Function P10 to P17 -- -- -- -- -- -- P04 -- -- --
3.1.2 PROM programming mode pins (PD78P014 only)
Pin Name Input/ Output RESET
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Function
Input
PROM programming mode setting. When +5 V or +12.5 V is applied to the VPP pin or a low-level voltage is applied to the RESET pin, the PROM programming mode is set.
VPP A0 to A14 D0 to D7
Input Input Input/ output
High-voltage application for PROM programming mode setting and program write/verify Address bus Data bus
CE OE VDD VSS
Input Input -- --
PROM enable input/program pulse input Read strobe input to PROM Positive power supply Ground potential
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3.2 Description of Pin Functions 3.2.1 P00 to P04 (Port 0) These are 5-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt request input, an external count clock input to the timer, a capture trigger signal input and crystal connection for subsystem clock oscillation. The following operating modes can be specified bit-wise. (1) Port mode P00 and P04 function as input-only ports and P01 to P03 function as input/output ports. P01 to P03 can be specified for input or output ports bit-wise with a port mode register 0 (PM0). When they are used as input ports, a pull-up resistor can be connected to them with an on-chip pull-up resistor option register (PUO). (2) Control mode In this mode, these ports function as an external interrupt request input, an external count clock input to the timer, and crystal connection for subsystem clock oscillation. (a) INTP0 to INTP3 INTP0 to INTP2 are external interrupt request input pins which can specify valid edges (rising edge, falling edge, and both rising and falling edges). INTP0 becomes a 16-bit timer/event counter capture trigger signal input pin with a valid edge input. INTP3 becomes a falling edge detection external interrupt request input pin.
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(b) TI0 TI0 is a pin for external count clock input to 16-bit timer/event counter. (c) XT1 Crystal connection pin for subsystem clock oscillation
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3.2.2 P10 to P17 (Port 1) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an A/D converter analog input. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with port mode register 1 (PM1). When used as an input port, an on-chip pull-up resistor can be connected to these ports with a pull-up resistor option register (PUO). (2) Control mode These ports function as A/D converter analog input pins (ANI0 to ANI7). If the pins are specified as analog input the on-chip pull-up resistor is automatically disabled.
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PIN FUNCTION (PD78014 Subseries)
3.2.3 P20 to P27 (Port 2) These are 8-bit input/output ports. Besides serving as input/output ports, they function as data input/output to/ from the serial interface, clock input/output, automatic transmit/receive busy input, and strobe output functions. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with a port mode register 2 (PM2). When they are used as input ports, an on-chip pull-up resistor can be connected to them with a pull-up resistor option register (PUO). (2) Control mode These ports function as serial interface data input/output, clock input/output, automatic transmit/receive busy input, and strobe output. (a) SI0, SI1, SO0, SO1 Serial interface serial data input/output pins (b) SCK0 and SCK1 Serial interface serial clock input/output pins (c) SB0 and SB1 NEC standard serial bus interface input/output pins (d) BUSY
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Serial interface automatic transmit/receive busy input pins (e) STB Serial interface automatic transmit/receive strobe output pins Caution When these ports are used as pins of serial interface, set the input/output and output latches depending on their functions. For the setting method, refer to Figure 15-5 Serial Operating Mode Register 0 Format and Figure 17-3 Serial Operating Mode Register 1 Format.
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3.2.4 P30 to P37 (Port 3) These are 8-bit input/output ports. Beside serving as input/output ports, they function as timer input/output, clock output and buzzer output. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with port mode register 3 (PM3). When they are used as input ports, an on-chip pull-up resistor can be connected with a pull-up resistor option register (PUO). (2) Control mode These ports function as timer input/output, clock output, and buzzer output. (a) TI1 and TI2 Pins for external count clock input to the 8-bit timer/event counter. (b) TO0 to TO2 Timer output pins (c) PCL Clock output pin (d) BUZ Buzzer output pin
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3.2.5 P40 to P47 (Port 4) These are 8-bit input/output ports. Besides serving as input/output ports, they function as address/data bus. Test input flag (KRIF) is set to 1 by falling edge detection. The following operating modes can be specified in 8-bit units. (1) Port mode These ports function as 8-bit input/output ports. They can be specified in 8-bit units as input or output ports with a memory expansion mode register (MM). When they are used as input ports, a pull-up resistor can be connected to them with an on-chip pull-up resistor option register (PUO). (2) Control mode These ports function as low-order address/data bus pins in external memory expansion mode. When they are used as address/data bus, an on-chip pull-up resistor is automatically unused. 3.2.6 P50 to P57 (Port 5) These are 8-bit input/output ports. Besides serving as input/output ports, they function as address/data bus. They can drive LEDs directly. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with port mode register 5 (PM5). When they are used as input ports, an on-chip pull-up resistor can be connected to them with a pull-up resistor option register (PUO).
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(2) Control mode These ports function as high-order address bus pins in external memory expansion mode. When they are used as address/data bus, the on-chip pull-up resistor is automatically disabled.
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3.2.7 P60 to P67 (Port 6) These are 8-bit output dedicated ports. Besides serving as input/output port, they have control functions in external memory expansion mode. P60 to P63 can drive LEDs directly. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports. They can be specified bit-wise for input or output ports by port mode register 6 (PM6). P60 to P63 are N-ch open-drain outputs. Mask ROM version can contain pull-up resistors with the mask option. When P64 to P67 are used as input ports, an on-chip pull-up resistor can be connected with a pull-up resistor option resistor (PUO). (2) Control mode These ports function as control signal output pins (RD, WR, WAIT, ASTB) in external memory expansion mode. When a pin is used as control signal output, the on-chip pull-up resistor is automatically disabled. Caution When external wait is not used in external memory expansion mode, P66 can be used as an input/ output port. 3.2.8 AVREF A/D converter reference voltage input pin. When the A/D converter is not used, connect it to VSS.
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3.2.9 AVDD Analog power supply pin of A/D converter. Always use the same voltage as that of the VDD pin even when A/D converter is not used. 3.2.10 AVSS This is a ground voltage pin of A/D converter. Always use the same voltage as that of the VSS pin even when A/D
converter is not used. 3.2.11 RESET This is a low-level active system reset input pin. 3.2.12 X1 and X2 Crystal resonator connection pins for main system clock oscillation. For external clock supply, input it to X1 and its inverted signal to X2.
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3.2.13 XT1 and XT2 Crystal resonator connection pins for subsystem clock oscillation. For external clock supply, input it to XT1 and its inverted signal to XT2. 3.2.14 VDD Positive power supply pin 3.2.15 VSS Ground potential pin 3.2.16 VPP (PD78P014 only) High-voltage apply pin for PROM programming mode setting and program write/verify. Connect directly to VSS in normal operating mode. 3.2.17 IC (Mask ROM version only) The IC (Internally Connected) pin sets a test mode in which the PD78011B, 78012B, 78013 and 78014 are tested before shipment. In normal operation mode, connect the IC pin directly to VSS with as short a wiring length as possible. If there is a potential difference between the IC and VSS pins because the wiring length between the IC and VSS pins is too long, or external noise is superimposed on the IC pin, your program may not run correctly.
* Directly connect the IC pin to the VSS.
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VSS
IC
shorten
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3.3 Input/Output Circuit and Recommended Connection of Unused Pins Table 3-1 shows the input/output circuit types of pins and the recommended conditions for unused pins. Refer to Figure 3-1 for the configuration of the input/output circuit of each type.
Table 3-1. Pin Input/Output Circuit Types (1/2)
Pin Name Input/Output Circuit Type P00/INTP0/TI0 P01/INTP1 P02/INTP2 P03/INTP3 P04/XT1 P10/ANI0 to P17/ANI7 P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P30/TO0
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Input/Output
Recommended Connection for Unused Pins
2 8-A
Input Input/output
Connect to VSS. Independently connect to VSS via a resistor.
16 11 8-A 5-A 8-A 5-A 8-A 10-A
Input Input/output
Connect to VDD or VSS. Independently connect to VDD or VSS via a resistor.
5-A
P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 P40/AD0 to P47/AD7 P50/A8 to P57/A15 P60 to P63 (Mask ROM Version) P60 to P63 (PROM Version) P64/RD P65/WR P66/WAIT P67/ASTB 5-A Independently connect to VDD or VSS via a resistor. 13 5-E 5-A 13-B Independently connect to VDD via a resistor. Independently connect to VDD or VSS via a resistor. Independently connect to VDD via a resistor. 5-A 8-A
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Table 3-1. Pin Input/Output Circuit Types (2/2)
Pin Name Input/Output Circuit Type RESET XT2 AVREF AVDD AVSS IC (Mask ROM Version) VPP (PROM Version) 2 16 -- Input -- -- Leave open Connect to VSS. Connect to VDD. Connect to VSS. Connect directly to VSS. Input/Output Recommended Connection for Unused Pins
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Figure 3-1. Pin Input/Output Circuit List (1/2)
Type 2
Type 8-A VDD
pull-up enable IN data VDD P-ch
P-ch
IN/OUT Schmitt-triggered input with hysteresis characteristics output disable N-ch
Type 5-A pull-up enable VDD data
VDD
Type 10-A
VDD
P-ch
pull-up enable VDD data IN/OUT P-ch
P-ch
P-ch
IN/OUT open-drain output disable N-ch
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output disable
N-ch
input enable Type 5-E VDD Type 11 pull-up enable VDD data P-ch IN/OUT IN/OUT output disable N-ch output disable P-ch Comparator + - N-ch VREF (threshold voltage) input enable N-ch VDD
pull-up enable VDD data P-ch
P-ch
P-ch
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Figure 3-1. Pin Input/Output Circuit List (2/2)
Type 13
Type 16 feedback cut-off P-ch
IN / OUT data output disable N-ch
XT1 Middle-High Voltage Input Buffer
XT2
Type 13-B VDD Mask Option IN / OUT data output disable N-ch VDD
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RD
P-ch
Middle-High Voltage Input Buffer
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[MEMO]
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PIN FUNCTION (PD78014Y Subseries)
4.1 Pin Function List 4.1.1 Normal operating mode pins (1) Port pins (1/2)
Pin Name
Input/ Output
Function
After Reset
Alternate Function INTP0/TI0 INTP1 INTP2 INTP3
P00 P01 P02 P03 P04Note 1 P10 to P17
Input Input/ Output
Port 0 5-bit input/output port
Input only Input/output specifiable bit-wise. If used as an input port, an on-chip pull-up resistor can be connected by software.
Input Input
Input Input/ Output Port 1 8-bit input/output port.
Input only
Input Input
XT1 ANI0 to ANI7
Input/output specifiable bit-wise. If used as an input port, an on-chip pull-up resistor can be connected by softwareNote 2. P20 P21
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Input/ Output
Port 2 8-bit input/output port. Input/output specifiable bit-wise. If used as an input port, an on-chip pull-up resistor can be connected by software.
Input
SI1 SO1 SCK1 STB BUSY SI0/SB0/SDA0 SO0/SB1/SDA1 SCK0/SC1
P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 Input/ Output
Port 3 8-bit input/output port. Input/output specifiable bit-wise. If used as an input port, an on-chip pull-up resistor can be connected by software.
Input
TO0 TO1 TO2 TI1 TI2 PCL BUZ --
Notes 1. When the P04/XT1 pin is used as an input port, set bit 6 (FRC) of the processor clock control register (PCC) to 1 (do not use the on-chip feedback resistor of the subsystem clock oscillator). 2. When pins P10/ANI0 to P17/ANI7 are used as analog input of the A/D converter, the on-chip pull-up resistor is automatically disabled.
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(1) Port pins (2/2)
Pin Name Input/ Output P40 to P47 Input/ Output Port 4 8-bit input/output port. Input/output specifiable in 8-bit units. When used as an input port, an on-chip pull-up resistor can be connected by software. Test input flag (KRIF) is set to 1 by falling edge detection. P50 to P57 Input/ Output Port 5 8-bit input/output port. LED can be driven directly. Input/output specifiable bit-wise. When used as an input port, an on-chip pull-up resistor can be connected by software. P60 P61 P62 P63 P64 P65 P66 P67
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Function
After Reset Input
Alternate Function AD0 to AD7
Input
A8 to A15
Input/ Output
Port 6 8-bit input/output port. Input/output specifiable bit-wise.
N-ch open drain input/output port. On-chip pull-up resistor can be specified by mask option. LED can be driven directly. When used as an input port, an on-chip pull-up resistor can be connected by software.
Input
--
RD WR WAIT ASTB
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(2) Non-Port Pins (1/2)
Pin Name Input/ Output INTP0 INTP1 INTP2 INTP3 SI0 SI1 SO0 SO1 SB0 SB1 SDA0 SDA1 SCK0 SCK1 SCL STB BUSY TI0 TI1 TI2
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Function
After Reset
Alternate Function P00/TI0 P01 P02
Input
External interrupt request inputs with specifiable valid edges (rising edge, falling edge, both rising and falling edges).
Input
External interrupt request input with falling edge detection. Input Serial interface serial data input
Input Input
P03 P25/SB0/SDA0 P20
Output
Serial interface serial data output
Input
P26/SB1/SDA1 P21
Input/ Output
Serial interface serial data input/output
Input
P25/SI0/SDA0 P26/SO0/SDA1 P25/SI0/SB0 P26/SO0/SB1
Input/ Output
Serial interface serial clock input/output
Input
P27/SCL P22 P27/SCK0
Output Input Input
Serial interface automatic transmit/receive strobe output Serial interface automatic transmit/receive busy input External count clock input to 16-bit timer (TM0) External count clock input to 8-bit timer (TM1) External count clock input to 8-bit timer (TM2)
Input Input Input
P23 P24 P00/INTP0 P33 P34
TO0 TO1 TO2 PCL BUZ AD0 to AD7
Output
16-bit timer (TM0) output (also used for 14-bit PWM output) 8-bit timer (TM1) output 8-bit timer (TM2) output
Input
P30 P31 P32
Output Output Input/ Output
Clock output (for main system clock and subsystem clock trimming) Buzzer output Low-order address/data bus at external memory expansion.
Input Input Input
P35 P36 P40 to P47
A8 to A15 RD WR WAIT ASTB
Output Output
High-order address bus at external memory expansion. External memory read operation strobe signal output. External memory write operation strobe signal output.
Input Input
P50 to P57 P64 P65
Input Output
Wait insertion at external memory access. Strobe output which latches the address data output for ports 4 or 5 to access external memory.
Input Input
P66 P67
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(2) Non-Port Pins (2/2)
Pin Name Input/ Output ANI0 to ANI7 AVREF AVDD AVSS RESET X1 X2 XT1 XT2 VDD VPP Input Input -- -- Input Input -- Input -- -- -- Positive power supply High-voltage application for program write/verify. Connect directly to VSS in normal operating mode. VSS IC -- -- Ground potential Internally connected. Directly connect to VSS. -- -- -- -- Crystal connection for subsystem clock oscillation A/D converter analog input. A/D converter reference voltage input. A/D converter analog power supply. Connect to VDD. A/D converter ground potential. Connect to VSS. System reset input Crystal connection for main system clock oscillation Function After Reset Input -- -- -- -- -- -- Input -- -- -- Alternate Function P10 to P17 -- -- -- -- -- -- P04 -- -- --
4.1.2 PROM programming mode pins (PD78P014Y only)
Pin Name Input/ Output RESET
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Function
Input
PROM programming mode setting. When +5 V or +12.5 V is applied to the VPP pin or a low-level voltage is applied to the RESET pin, the PROM programming mode is set.
VPP A0 to A14 D0 to D7
Input Input Input/ output
High-voltage application for PROM programming mode setting and program write/verify Address bus Data bus
CE OE VDD VSS
Input Input -- --
PROM enable input/program pulse input Read strobe input to PROM Positive power supply Ground potential
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4.2 Description of Pin Functions 4.2.1 P00 to P04 (Port 0) These are 5-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt request input, an external count clock input to the timer, a capture trigger signal input and crystal connection for subsystem clock oscillation. The following operating modes can be specified bit-wise. (1) Port mode P00 and P04 function as input-only ports and P01 to P03 function as input/output ports. P01 to P03 can be specified for input or output ports bit-wise with port mode register 0 (PM0). When they are used as input ports, a pull-up resistor can be connected to them with an on-chip pull-up resistor option register (PUO). (2) Control mode In this mode, these ports function as an external interrupt request input, an external count clock input to the timer, and crystal connection for subsystem clock oscillation. (a) INTP0 to INTP3 INTP0 to INTP2 are external interrupt request input pins which can specify valid edges (rising edge, falling edge, and both rising and falling edges). INTP0 become a 16-bit timer/event counter capture trigger signal input pin with a valid edge input. INTP3 become a falling edge detection external interrupt request input pin.
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(b) TI0 TI0 is a pin for external count clock input to 16-bit timer/event counter. (c) XT1 Crystal connection pin for subsystem clock oscillation
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4.2.2 P10 to P17 (Port 1) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an A/D converter analog input. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with port mode register 1 (PM1). When used as input ports, an on-chip pull-up resistor can be connected to these ports with a pull-up resistor option register (PUO). (2) Control mode These ports function as A/D converter analog input pins (ANI0 to ANI7). If the pins are specified as analog input, the on-chip pull-up resistor is automatically disabled.
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4.2.3 P20 to P27 (Port 2) These are 8-bit input/output ports. Besides serving as input/output ports, they function as data input/output to/ from the serial interface, clock input/output, automatic transmit/receive busy input, and strobe output. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with port mode register 2 (PM2). When they are used as input ports, an on-chip pull-up resistor can be connected to them with a pull-up resistor option register (PUO). (2) Control mode These ports function as serial interface data input/output, clock input/output, automatic transmit/receive busy input, and strobe output. (a) SI0, SI1, SO0, SO1, SDA0, SDA1 Serial interface serial data input/output pins (b) SCK0, SCK1, SCL Serial interface serial clock input/output pins (c) SB0 and SB1 NEC standard serial bus interface input/output pins (d) BUSY
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Serial interface automatic transmit/receive busy input pins (e) STB Serial interface automatic transmit/receive strobe output pins Caution When these ports are used as pins of serial interface, set the input/output and output latches depending on their functions. For the setting method, refer to Figure 16-6 Serial Operating Mode Register 0 Format and Figure 17-3 Serial Operating Mode Register 1 Format.
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4.2.4 P30 to P37 (Port 3) These are 8-bit input/output ports. Beside serving as input/output ports, they function as timer input/output, clock output and buzzer output. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with port mode register 3 (PM3). When they are used as input ports, an on-chip pull-up resistor can be connected with a pull-up resistor option register (PUO). (2) Control mode These ports function as timer input/output, clock output, and buzzer output. (a) TI1 and TI2 Pins for external count clock input to the 8-bit timer/event counter. (b) TO0 to TO2 Timer output pins (c) PCL Clock output pin (d) BUZ Buzzer output pin
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4.2.5 P40 to P47 (Port 4) These are 8-bit input/output ports. Besides serving as input/output ports, they function as address/data bus. The test input flag (KRIF) is set to 1 by falling edge detection. The following operating modes can be specified in 8-bit units. (1) Port mode These ports function as 8-bit input/output ports. They can be specified in 8-bit units as input or output ports with a memory expansion mode register (MM). When they are used as input ports, a pull-up resistor can be connected to them with an on-chip pull-up resistor option register (PUO). (2) Control mode These ports function as low-order address/data bus pins in external memory expansion mode. When they are used as address/data bus, the on-chip pull-up resistor is automatically disabled. 4.2.6 P50 to P57 (Port 5) These are 8-bit input/output ports. Besides serving as input/output ports, they function as address/data bus. They can drive LEDs directly. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports. They can be specified bit-wise as an input or output ports with port mode register 5 (PM5). When they are used as input ports, an on-chip pull-up resistor can be connected to them with a pull-up resistor option register (PUO).
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(2) Control mode These ports function as high-order address/data bus pins (A8 to A15) in external memory expansion mode. When they are used as address bus, the on-chip pull-up resistor is automatically disabled.
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4.2.7 P60 to P67 (Port 6) These are 8-bit input/output ports. Besides serving as an input/output port, they have control functions in external memory expansion mode. P60 to P63 can drive LEDs directly. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports by port mode register 6 (PM6). P60 to P63 are N-ch open-drain outputs. Mask ROM versions can contain pull-up resistors with the mask option. When P64 to P67 are used as input ports, an on-chip pull-up resistor can be connected with a pull-up resistor option resistor (PUO). (2) Control mode These ports function as control signal output pins (RD, WR, WAIT, ASTB) in external memory expansion mode. When a pin is used as control signal output, the on-chip pull-up resistor is automatically disabled. Caution When external wait is not used in external memory expansion mode, P66 can be used as an input/ output port. 4.2.8 AVREF A/D converter reference voltage input pin. When the A/D converter is not used, connect it to the VSS.
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4.2.9 AVDD Analog power supply pin of A/D converter. Always use the same voltage as that of the VDD pin even when A/D converter is not used. 4.2.10 AVSS This is a ground voltage pin of A/D converter. Always use the same voltage as that of the VSS pin even when A/D converter is not used.
4.2.11 RESET This is a low level active system reset input pin. 4.2.12 X1 and X2 Crystal resonator connection pins for main system clock oscillation. For external clock supply, input it to X1 and its inverted signal to X2.
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4.2.13 XT1 and XT2 Crystal resonator connection pins for subsystem clock oscillation. For external clock supply, input it to XT1 and its inverted signal to XT2. 4.2.14 VDD Positive power supply pin 4.2.15 VSS Ground potential pin 4.2.16 VPP (PD78P014Y only) High-voltage apply pin for PROM programming mode setting and program write/verify. Connect directly to VSS in normal operating mode. 4.2.17 IC (Mask ROM versions only) The IC (Internally Connected) pin sets a test mode in which the PD78011BY, 78012BY, 78013Y and 78014Y are tested before shipment. In normal operation mode, connect the IC pin directly to VSS with as short a wiring length as possible. If there is a potential difference between the IC and VSS pins because the wiring length between the IC and VSS pin is too long, or external noise is superimposed on the IC pin, your program may not run correctly.
* Directly connect the IC pin to the VSS.
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VSS IC
shorten
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4.3 Input/Output Circuit and Recommended Connection of Unused Pins Table 4-1 shows the input/output circuit types of pins and the recommended conditions for unused pins. Refer to Figure 4-1 for the configuration of the input/output circuit of each type.
Table 4-1. Pin Input/Output Circuit Types (1/2)
Pin Name Input/Output Input/Output Circuit Type P00/INTP0/TI0 P01/INTP1 P02/INTP2 P03/INTP3 P04/XT1 P10/ANI0 to P17/ANI7 P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0/SDA0 P26/SO0/SB1/SDA1 P27/SCK0/SCL P30/TO0
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Recommended Connection for Unused Pins
2 8-A
Input Input/output
Connect to VSS. Independently connect to VSS via a resistor.
16 11 8-A 5-A 8-A 5-A 8-A 10-A
Input Input/output
Connect to VDD or VSS. Independently connect to VDD or VSS via a resistor.
5-A
P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 P40/AD0 to P47/AD7 P50/A8 to P57/A15 P60 to P63 (Mask ROM Version) P60 to P63 (PROM Version) P64/RD P65/WR P66/WAIT P67/ASTB 5-A Independently connect to VDD or VSS via a resistor. 13 5-E 5-A 13-B Independently connect to VDD via a resistor. Independently connect to VDD or VSS via a resistor. Independently connect to VDD via a resistor. 5-A 8-A
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Table 4-1. Pin Input/Output Circuit Types (2/2)
Pin Name Input/Output Input/Output Circuit Type RESET XT2 AVREF AVDD AVSS IC (Mask ROM Version) VPP (PROM Version) 2 16 -- Input -- -- Leave open Connect to VSS. Connect to VDD. Connect to VSS. Connect directly to VSS. Recommended Connection for Unused Pins
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Figure 4-1. Pin Input/Output Circuit List (1/2)
Type 2
Type 8-A VDD
pull-up enable IN data VDD P-ch
P-ch
IN/OUT Schmitt-triggered input with hysteresis characteristics output disable N-ch
Type 5-A pull-up enable VDD data
VDD
Type 10-A
VDD
P-ch
pull-up enable VDD data IN/OUT P-ch
P-ch
P-ch
IN/OUT open-drain output disable N-ch
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output disable
N-ch
input enable Type 5-E VDD Type 11 pull-up enable VDD data P-ch IN/OUT IN/OUT output disable N-ch output disable P-ch Comparator + - N-ch VREF (threshold voltage) input enable N-ch VDD
pull-up enable VDD data P-ch
P-ch
P-ch
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Figure 4-1. Pin Input/Output Circuit List (2/2)
Type 13
Type 16 feedback cut-off P-ch
IN / OUT data output disable N-ch
XT1 Middle-High Voltage Input Buffer
XT2
Type 13-B VDD Mask Option IN / OUT data output disable N-ch VDD
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RD
P-ch
Middle-High Voltage Input Buffer
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[MEMO]
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CHAPTER 5
CPU ARCHITECTURE
CHAPTER 5
CPU ARCHITECTURE
5.1 Memory Spaces The PD78014 and 78014Y Subseries can each access a memory space of 64 Kbytes. Figures 5-1 to 5-5 show memory maps.
Figure 5-1. Memory Map (PD78011B, 78011BY)
FFFFH Special Function Registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH Internal High-Speed RAM 512 x 8 bits General Registers 32 x 8 bits
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Data Memory Space
FD00H FCFFH FAE0H FADFH FAC0H FABFH
1FFFH Use Prohibited Buffer RAM 32 x 8 bits 1000H 0FFFH CALLF Entry Area Use Prohibited 0800H 07FFH Program Area External Memory 55936 x 8 bits 0080H 007FH CALLT Table Area 0040H 003FH Vector Table Area Program Area
FA80H FA7FH
Program Memory Space
2000H 1FFFH Internal ROM 8192 x 8 bits
0000H
0000H
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Figure 5-2. Memory Map (PD78012B, 78012BY)
FFFFH Special Function Registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH Internal High-Speed RAM 512 x 8 bits General Registers 32 x 8 bits
FD00H FCFFH FAE0H FADFH FAC0H FABFH
3FFFH Use Prohibited Buffer RAM 32 x 8 bits 1000H 0FFFH CALLF Entry Area Use Prohibited 0800H 07FFH Program Area External Memory 47744 x 8 bits 0080H 007FH CALLT Table Area 0040H 003FH Vector Table Area Program Area
Data Memory Space
FA80H FA7FH
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Program Memory Space
4000H 3FFFH Internal ROM 16384 x 8 bits
0000H
0000H
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Figure 5-3. Memory Map (PD78013, 78013Y)
FFFFH Special Function Registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH Internal High-Speed RAM 1024 x 8 bits General Registers 32 x 8 bits
FB00H FAFFH FAE0H Data Memory Space FADFH FAC0H FABFH Use Prohibited Buffer RAM 32 x 8 bits
5FFFH Program Area 1000H 0FFFH CALLF Entry Area Use Prohibited 0800H 07FFH Program Area External Memory 39552 x 8 bits 0080H 007FH CALLT Table Area 0040H 003FH Vector Table Area
FA80H FA7FH
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Program Memory Space
6000H 5FFFH Internal ROM 24576 x 8 bits
0000H
0000H
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Figure 5-4. Memory Map (PD78014, 78014Y)
FFFFH Special Function Registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH Internal High-Speed RAM 1024 x 8 bits General Registers 32 x 8 bits
FB00H FAFFH FAE0H FADFH FAC0H FABFH Use Prohibited Buffer RAM 32 x 8 bits
7FFFH Program Area 1000H 0FFFH CALLF Entry Area Use Prohibited 0800H 07FFH Program Area External Memory 31360 x 8 bits 0080H 007FH CALLT Table Area 0040H 003FH Vector Table Area
Data Memory Space
FA80H FA7FH
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Program Memory Space
8000H 7FFFH Internal ROM 32768 x 8 bits
0000H
0000H
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Figure 5-5. Memory Map (PD78P014, 78P014Y)
FFFFH Special Function Registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH Internal High-Speed RAM 1024 x 8 bits General Registers 32 x 8 bits
FB00H FAFFH FAE0H Data Memory Space FADFH FAC0H FABFH Use Prohibited Buffer RAM 32 x 8 bits
7FFFH Program Area 1000H 0FFFH CALLF Entry Area Use Prohibited 0800H 07FFH Program Area External Memory 31360 x 8 bits 0080H 007FH CALLT Table Area 0040H 003FH Vector Table Area
FA80H FA7FH
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Program Memory Space
8000H 7FFFH Internal ROM 32768 x 8 bits
0000H
0000H
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5.1.1 Internal program memory space Internal program memory store programs and table data. Normally, they are addressed with a program counter (PC). The PD78014 and 78014Y Subseries contain internal ROM (or PROM) in each product having the capacities shown below.
Table 5-1. Internal ROM Capacity
Part Number Internal ROM Configuration Capacity 8192 x 8 bits 16384 x 8 bits 24576 x 8 bits 32768 x 8 bits PROM
PD78011B, 78011BY PD78012B, 78012BY PD78013, 78013Y PD78014, 78014Y PD78P014, 78P014Y
Mask ROM
The following areas are allocated in the internal program memory space. (1) Vector table area The 64-byte area 0000H to 003FH is reserved as vector table area. The RESET input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area. Of the 16bit address, the low-order 8 bits are stored at even addresses and the high-order 8 bits are stored at odd addresses.
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Table 5-2. Vector Table
Vector Table Address 0000H 0004H 0006H 0008H 000AH 000CH 000EH Interrupt Source RESET input INTWDT INTP0 INTP1 INTP2 INTP3 INTCSI0 Vector Table Address 0010H 0012H 0014H 0016H 0018H 001AH 003EH Interrupt Source INTCSI1 INTTM3 INTTM0 INTTM1 INTTM2 INTAD BRK Instruction
(2) CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) CALLF instruction entry area The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).
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5.1.2 Internal data memory space The PD78014 and 78014Y Subseries incorporate the following RAMs. (1) Internal high-speed RAM The PD78014 and 78014Y Subseries incorporate the following capacity of internal high-speed RAM in each product.
Table 5-3. Internal High-Speed RAM Capacities
Part Number Internal High-speed RAM Capacity 512 x 8 bits 1024 x 8 bits
PD78011B, 78011BY PD78012B, 78012BY PD78013, 78013Y PD78014, 78014Y PD78P014, 78P014Y
4 banks of general registers, each bank consisting of eight 8-bit registers are allocated in the 32-byte area FEE0H to FEFFH. The internal high-speed RAM can also be used as a stack memory area. (2) Buffer RAM Buffer RAM is allocated to the 32-byte area from FAC0H to FADFH. Buffer RAM is used for storing transmit/
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receive data of serial interface channel 1 (3-wire serial I/O mode with automatic transmit/receive function). When not used in the 3-wire serial I/O mode with automatic transmit/receive function, buffer RAM can also be used as normal RAM. 5.1.3 Special function register (SFR) area An on-chip peripheral hardware special-function register (SFR) is allocated in the area FF00H to FFFFH (refer to Table 5-5. Special Function Register List of 5.2.3 Special function register (SFR)). Caution Do not access addresses where the SFR is not assigned.
5.1.4 External memory space External memory space that can be accessed by setting a memory expansion mode register (MM). Program and table data can be stored, and peripheral devices can be allocated.
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5.2 Processor Registers The PD78014 and 78014Y Subseries incorporate the following processor registers. 5.2.1 Control registers The control registers control the program sequence, statuses and stack memory. A program counter (PC), a program status word (PSW) and a stack pointer (SP) are control registers. (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed. In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data and register contents are set. RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.
Figure 5-6. Program Counter Configuration
15 PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
(2) Program status word (PSW) The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically reset upon execution of the RETB, RETI and POP PSW instructions. RESET input sets the PSW to 02H.
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Figure 5-7. Program Status Word Configuration
7 PSW IE Z RBS1 AC RBS0 0 ISP 0 CY
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(a) Interrupt enable flag (IE) This flag controls interrupt request acknowledge operations of CPU. When IE = 0, the IE is set to interrupt disabled (DI) status. All interrupt requests except non-maskable interrupt are disabled. When IE = 1, the IE is set to interrupt enabled (EI) status and interrupt request acknowledgement is controlled with an inservice priority flag (ISP), an interrupt mask flag for various interrupt sources and a priority specification flag. This flag is reset to (0) upon DI instruction execution or interrupt request acknowledgment and is set to (1) upon EI instruction execution. (b) Zero flag (Z) When the operation result is zero, this flag is set to (1). It is reset to (0) in all other cases. (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information which indicates the register bank selected by SEL RBn instruction execution is stored. (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to (1). It is reset to (0) in all other cases. (e) In-service priority flag (ISP) This flag manages the priority of acknowledgeable maskable vectored interrupts.
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When ISP = 0, acknowledgment of the vectored interrupt request specified to low-order priority with the priority specify flag registers (PR0L and PR0H) (refer to 18.3 (3) Priority specify flag registers (PR0L, PR0H)) is disabled. Whether an actual interrupt request is acknowledged or not is controlled with the interrupt enable flag (IE). (f) Carry flag (CY) This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution.
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(3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Internal high-speed RAM of each product is as follows.
PD78011B, 78011BY, 78012B, 78012BY: FD00H to FEFFH PD78013, 78013Y, 78014, 78014Y, 78P014, 78P014Y: FB00H to FEFFH
Figure 5-8. Stack Pointer Configuration
15 SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8
0 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory. Each stack operation saves/resets data as shown in Figures 5-9 and 5-10. Caution Since SP contents will be undefined by RESET input, be sure to initialize the SP before instruction execution.
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Figure 5-9. Data to be Saved to Stack Memory
PUSH rp Instruction
CALL, CALLF, and CALLT Instruction SPSP-3
Interrupt and BRK Instruction
SPSP-2 SP-2 SP-1 SP Register Pair Upper Register Pair Lower
SPSP-2 SP-2 SP-1 SP PC15 to PC8 PC7 to PC0
SP-3 SP-2 SP-1 SP
PC7 to PC0 PC15 to PC8 PSW
Figure 5-10. Data to be Reset from Stack Memory
POP rp Instruction RET Instruction RETI and RETB Instruction
SP SP+1
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Register Pair Lower Register Pair Upper
SP SP+1 SPSP+2
PC7 to PC0 PC15 to PC8
SP SP+1 SP+2 SPSP+3
PC7 to PC0 PC15 to PC8 PSW
SPSP+2
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5.2.2 General registers A general register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L and H). Each register can also be used as an 8-bit register. Two 8-bit registers can be used in pairs as a 16-bit register (AX, BC, DE and HL). They can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE and HL) and absolute names (R0 to R7 and RP0 to RP3). Register banks to be used for instruction execution are set with the CPU control instruction (SEL RBn). Because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interrupt request for each bank.
Table 5-4. Absolute Address Corresponding to General Registers
Bank Name BANK0
Register Function Name H L D E B C A X Absolute Name R7 R6 R5 R4 R3 R2 R1 R0 R7 R6 R5 R4 R3 R2 R1 R0
Absolute Address FEFFH FEFEH FEFDH FEFCH FEFBH FEFAH FEF9H FEF8H FEF7H FEF6H FEF5H FEF4H FEF3H FEF2H FEF1H FEF0H
Bank Name BANK2
Register Function Name H L D E B C A X Absolute Name R7 R6 R5 R4 R3 R2 R1 R0 R7 R6 R5 R4 R3 R2 R1 R0
Absolute Address FEEFH FEEEH FEEDH FEECH FEEBH FEEAH FEE9H FEE8H FEE7H FEE6H FEE5H FEE4H FEE3H FEE2H FEE1H FEE0H
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BANK1
H L D E B C A X
BANK3
H L D E B C A X
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Figure 5-11. General Register Configuration
(a) Absolute Name
16-Bit Processing FEFFH
8-Bit Processing R7
BANK0 FEF8H FEF7H BANK1 FEF0H FEEFH BANK2 FEE8H FEE7H BANK3 FEE0H 15
RP3 R6 R5 RP2 R4 R3 RP1 R2 R1 RP0 R0 0 7 0
(b) Function Name
16-Bit Processing FEFFH
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8-Bit Processing H
BANK0 FEF8H FEF7H BANK1 FEF0H FEEFH BANK2 FEE8H FEE7H BANK3 FEE0H 15
HL L D DE E B BC C A AX X 0 7 0
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5.2.3 Special function register (SFR) Unlike a general register, each special function register has special functions. It is allocated in the FF00H to FFFFH area. The special function register can be manipulated, like the general register, with the operation, transfer and bit manipulation instructions. Manipulatable bit units, 1, 8 and 16, depend on the special function register type. Each manipulation bit unit can be specified as follows. * 1-bit manipulation Describes the symbol reserved with assembler for the 1 bit manipulation instruction operand (sfr.bit). This manipulation can also be specified with an address. * 8-bit manipulation Describes the symbol reserved with assembler for the 8-bit manipulation instruction operand (sfr). This manipulation can also be specified with an address. * 16-bit manipulation Describes the symbol reserved with assembler for the 16-bit manipulation instruction operand (sfrp). When addressing an address, describe an even address. Table 5-5 gives a list of special function registers. The meaning of items in the table is as follows. * Symbols A symbol indicates an address of the special function register. Symbols are reserved words in RA78K/0 and have been defined by a header file sfrbt.h in CC78K/0. They can be used as instruction operands when RA78K/0, ID78K0, or SD78K/0 is used. * R/W
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Indicates whether the corresponding special function register can be read or written. R/W : Read/write enable R W : Read only : Write only
* Manipulatable bit units The register can be manipulated in bit units (1, 8, and 16) marked with " ". The register cannot be manipulated in bit units marked with "--". * When reset Indicates each register status upon RESET input.
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Table 5-5. Special Function Register List (1/2)
Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit 1 Bit 8 Bits 16 Bits FF00H FF01H FF02H FF03H FF04H FF05H FF06H FF10H FF11H FF12H FF13H FF14H FF15H FF16H FF17H FF18H FF19H FF1AH FF1BH
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When Reset
Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 16-bit compare register
P0 P1 P2 P3 P4 P5 P6 CR00
R/W
-- -- -- -- -- -- -- -- --
00H
Undefined
16-bit capture register
CR01
R
--
--
16-bit timer register
TM0
--
--
0000H
8-bit compare register 8-bit compare register 8-bit timer register 1 8-bit timer register 2 Serial I/O shift register 0 Serial I/O shift register 1 A/D conversion result register Port mode register 0 Port mode register 1 Port mode register 2 Port mode register 3 Port mode register 5 Port mode register 6 Timer clock select register 0 Timer clock select register 1 Timer clock select register 2 Timer clock select register 3 Sampling clock select register 16-bit timer mode control register 8-bit timer mode control register Watch timer mode control register 16-bit timer output control register 8-bit timer output control register
CR10 CR20 TMS TM1 TM2 SIO0 SIO1 ADCR PM0 PM1 PM2 PM3 PM5 PM6 TCL0 TCL1 TCL2 TCL3 SCS TMC0 TMC1 TMC2 TOC0 TOC1
R/W
-- --
-- --
Undefined
R
-- --
00H
R/W
-- --
-- -- -- -- -- -- -- -- -- --
Undefined
FF1FH FF20H FF21H FF22H FF23H FF25H FF26H FF40H FF41H FF42H FF43H FF47H FF48H FF49H FF4AH FF4EH FF4FH
R R/W
--
1FH FFH
00H
-- -- -- --
-- -- -- -- -- -- -- -- -- 88H 00H
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Table 5-5. Special Function Register List (2/2)
Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit 1 Bit 8 Bits 16 Bits FF60H FF61H FF62H FF63H FF68H FF69H FF6AH FF80H FF84H FFD0H to FFDFH FFE0H FFE1H FFE4H FFE5H FFE8H FFE9H FFECH
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When Reset
Serial operating mode register 0 Serial bus interface control register Slave address register Interrupt timing specify register Serial operating mode register 1 Automatic data transmit/receive control register Automatic data transmit/receive address pointer A/D converter mode register A/D converter input select register External access areaNote 1
CSIM0 SBIC SVA SINT CSIM1 ADTC ADTP ADM ADIS
R/W
-- -- -- -- -- -- -- -- -- -- -- -- --
00H
Undefined 00H
01H 00H Undefined
Interrupt request flag register 0L Interrupt request flag register 0H Interrupt mask flag register 0L Interrupt mask flag register 0H Priority specify flag register 0L Priority specify flag register 0H External interrupt mode register Internal memory size switching register Key return mode register Pull-up resistor option register Memory expansion mode register Watchdog timer mode register Oscillation stabilization time select register Processor clock control register
IF0
IF0L IF0H
00H
MK0 MK0L MK0H PR0 PR0L PR0H INTM0 IMS KRM PUO MM WDTM OSTS PCC -- W R/W -- -- -- -- -- -- -- -- -- --
FFH
00H Note 2 02H 00H 10H 00H 04H
FFF0H FFF6H FFF7H FFF8H FFF9H FFFAH FFFBH
Notes 1. The external access area cannot be accessed in SFR addressing. Access the area with the direct addressing. 2. The value when reset depends on products.
PD78011B, 78011BY: 42H, PD78012B, 78012BY: 44H, PD78013, 78013Y: C6H, PD78014, 78014Y, 78P014, 78P014Y: C8H
If using the mask ROM version, do not set any value other than that when reset to IMS.
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5.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, however, the branch destination information is set to the PC and branched by the following addressing (For details of instructions, refer to 78K/0 Series User's Manual, Instructions (U12326E). 5.3.1 Relative addressing [Function] The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (PC) and branched. The displacement value is treated as signed two's complement data (-128 to +127) and bit 7 becomes a sign bit. In other words, the range of branch in relative addressing is between -128 and +127 of the start address of the following instruction. This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed. [Illustration]
15 PC + 15
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0 PC indicates the start address of the instruction after the BR instruction
8
7 S
6
0
jdisp8 15 PC When S = 0, all bits of are 0. When S = 1, all bits of are 1. 0
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5.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL ! addr16, BR ! addr16, or CALLF ! addr11 instruction is executed. CALL ! addr16 and BR ! addr16 instructions can branch to all the memory spaces. CALLF ! addr11 instruction branches to the area from 0800H to 0FFFH. [Illustration] In the case of CALL ! addr16 and BR ! addr16 instructions
7 CALL or BR Low Addr. High Addr. 0
15 PC
8
7
0
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In the case of CALLF ! addr11 instruction
7
6 fa10-8
43 CALLF fa7-0
0
15 PC 0 0 0 0
11 10 1
87
0
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5.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. Table indirect addressing is carried out when the CALLT [addr5] instruction is executed. This instruction can refer to the address stored in the memory table 40H to 7FH and branch to all the memory spaces. [Illustration]
7 Operation Code 1
6 1
5 ta4-0
1
0 1
15 Effective Address 0 0 0 0 0 0 0
8 0
7 0
6 1
5
10 0
7
Memory (Table) Low Addr.
0
Effective Address+1
High Addr.
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15 PC
8
7
0
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5.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration]
7 rp A
0
7 X
0
15 PC
8
7
0
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5.4 Operand Address Addressing 5.4.1 Data memory addressing Addressing is a method to specify the instruction address to be executed next and the register and memory address to be manipulated when instructions are executed. The instruction address to be executed next is addressed by the program counter (PC) (for details, refer to 5.3 Instruction Address Addressing). For the addressing of the memory to be manipulated when instructions are executed, the PD78014 and 78014Y Subseries are provided with several addressing modes which take account of optimum manipulability. In particular, specific types of addressing can be used which match the functions of the special function registers (SFRs), general registers, etc. Data memory addressing is shown in Figures 5-12 to 5-16.
Figure 5-12. Data Memory Addressing (PD78011B, 78011BY)
FFFFH Special Function Registers (SFR) 256 x 8 bits FF20H FF1FH FF00H FEFFH General Registers 32 x 8 bits FEE0H FEDFH Internal High-Speed RAM 512 x 8 bits
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SFR addressing
Register addressing
Short direct addressing
FE20H FE1FH Direct addressing FD00H FCFFH FAE0H FADFH FAC0H FABFH Use Prohibited Based addressing Buffer RAM 32 x 8 bits Based indexed addressing Register indirect addressing
Use Prohibited FA80H FA7FH External Memory 55936 x 8 bits
2000H 1FFFH Internal ROM 8192 x 8 bits
0000H
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Figure 5-13. Data Memory Addressing (PD78012B, 78012BY)
FFFFH Special Function Registers (SFR) 256 x 8 bits FF20H FF1FH FF00H FEFFH General Registers 32 x 8 bits FEE0H FEDFH Internal High-Speed RAM 512 x 8 bits FE20H FE1FH Direct addressing FD00H FCFFH FAE0H FADFH FAC0H FABFH Use Prohibited Based addressing Buffer RAM 32 x 8 bits Based indexed addressing Register indirect addressing Register addressing Short direct addressing SFR addressing
Use Prohibited FA80H FA7FH
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External Memory 47744 x 8 bits
4000H 3FFFH Internal ROM 16384 x 8 bits
0000H
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Figure 5-14. Data Memory Addressing (PD78013, 78013Y)
FFFFH Special Function Registers (SFR) 256 x 8 bits FF20H FF1FH FF00H FEFFH General Registers 32 x 8 bits FEE0H FEDFH Internal High-Speed RAM 1024 x 8 bits FE20H FE1FH Direct addressing FB00H FAFFH FAE0H FADFH FAC0H FABFH Use Prohibited Based addressing Buffer RAM 32 x 8 bits Based indexed addressing Register indirect addressing Register addressing Short direct addressing SFR addressing
Use Prohibited FA80H FA7FH
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External Memory 39552 x 8 bits
6000H 5FFFH Internal ROM 24576 x 8 bits
0000H
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Figure 5-15. Data Memory Addressing (PD78014, 78014Y)
FFFFH Special Function Registers (SFR) 256 x 8 bits FF20H FF1FH FF00H FEFFH General Registers 32 x 8 bits FEE0H FEDFH Internal High-Speed RAM 1024 x 8 bits FE20H FE1FH Direct addressing FB00H FAFFH FAE0H FADFH FAC0H FABFH Use Prohibited Based addressing Buffer RAM 32 x 8 bits Based indexed addressing Register indirect addressing Register addressing Short direct addressing SFR addressing
Use Prohibited FA80H FA7FH
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External Memory 31360 x 8 bits
8000H 7FFFH Internal ROM 32768 x 8 bits
0000H
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Figure 5-16. Data Memory Addressing (PD78P014, 78P014Y)
FFFFH Special Function Registers (SFR) 256 x 8 bits FF20H FF1FH FF00H FEFFH General Registers 32 x 8 bits FEE0H FEDFH Internal High-Speed RAM 1024 x 8 bits FE20H FE1FH Direct addressing FB00H FAFFH FAE0H FADFH FAC0H FABFH Use Prohibited Based addressing Buffer RAM 32 x 8 bits Based indexed addressing Register indirect addressing Register addressing Short direct addressing SFR addressing
Use Prohibited FA80H FA7FH
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External Memory 31360 x 8 bits
8000H 7FFFH Internal PROM 32768 x 8 bits
0000H
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5.4.2 Implied addressing [Function] The register which functions as an accumulator (A and AX) in the general register is automatically (implicitly) addressed. Of the PD78014 and 78014Y Subseries instruction words, the following instructions employ implied addressing.
Instruction MULU DIVUW ADJBA/ADJBS ROR4/ROL4 Register to be Specified by Implied Addressing A register for multiplicand and AX register for product storage AX register for dividend and quotient storage A register for storage of numeric values subject to decimal adjustment A register for storage of digit data which undergoes digit rotation
[Operand format] Because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [Description example] In the case of MULU X With an 8-bit x 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example, the A and AX registers are specified by implied addressing.
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5.4.3 Register addressing [Function] The general register is accessed as an operand. The general register to be accessed is specified with register bank select flags (RBS0 and RBS1) and register specify code (Rn and RPn) in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [Operand format]
Identifier r rp Description X, A, C, B, E, D, L, H AX, BC, DE, HL
`r' and `rp' can be described with function names (X, A, C, B, E, D, L, H, AX, BC, DE and HL) as well as absolute names (R0 to R7 and RP0 to RP3). [Description example] MOV A, C; when selecting C register as r
Instruction code
0
1
1
0
0
0
1
0 Register specify code
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INCW DE; when selecting DE register pair as rp
Instruction code 1 0 0 0 0 1 0 0 Register specify code
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5.4.4 Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed. [Operand format] Identifier
addr16 Description Label or 16-bit immediate data
[Description example] MOV A, ! 0FE00H; when setting ! addr16 to FE00H
Instruction code
1
0
0
0
1
1
1
0
OP code
0
0
0
0
0
0
0
0
00H
1
1
1
1
1
1
1
0
FEH
[Illustration]
7 OP code addr16 (lower)
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0
addr16 (higher) Memory
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5.4.5 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space where this addressing is applied to is the 256-byte space FE20H to FF1FH. An internal highspeed RAM and a special function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively. The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of all SFR areas. In this area, ports which are frequently accessed in a program and a compare register of the timer/event counter and a capture register of the timer/event counter are mapped and these SFRs can be manipulated with a small number of bytes and clocks. When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH, bit 8 is set to 1. Refer to [Illustration] on next page. [Operand format]
Identifier saddr saddrp Description Label or FE20H to FF1FH immediate data Label or FE20H to FF1FH immediate data (even address only)
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[Description example] MOV 0FE30H, #50H; when setting saddr to FE30H and immediate data to 50H
Instruction code 0 0 0 1 0 0 0 1 OP code
0
0
1
1
0
0
0
0
30H (saddr-offset)
0
1
0
1
0
0
0
0
50H (immediate data)
[Illustration]
7 OP code saddr-offset 0
Short Direct Memory 15 Effective address 1 1 1 1 1 1 1 8 0
When 8-bit immediate data is 20H to FFH, = 0 When 8-bit immediate data is 00H to 1FH, = 1
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5.4.6 Special function register (SFR) addressing [Function] The memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR mapped at FF00H to FF1FH can also be accessed with short direct addressing. [Operand format]
Identifier sfr sfrp Special function register name 16-bit manipulatable special function register name (even address only) Description
[Description example] MOV PM0, A; when selecting PM0 (FF20H) as sfr
Instruction code 1 1 1 1 0 1 1 0 OP code
0
0
1
0
0
0
0
0
20H (sfr-offset)
[Illustration]
7
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0 OP code sfr-offset
15 Effective address 1 1 1 1 1 1 1
87 1
0
SFR
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5.4.7 Register indirect addressing [Function] The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register bank select flag (RBS0 and RBS1) and the register pair specify code in the instruction code. This addressing can be carried out for all the memory spaces. [Operand format]
Identifier -- [DE], [HL] Description
[Description example] MOV A, [DE]; when selecting [DE] as register pair
Instruction code 1 0 0 0 0 1 0 1
[Illustration]
15 DE D
87 E
0
7
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Memory
0
Memory address specified by register pair DE
The contents of addressed memory are transferred 7 A 0
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5.4.8 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. The HL register pair to be accessed is in the register bank specified with the register bank select flags (RBS0 and RBS1). The offset data as a positive number is expanded to 16 bits to be added. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format]
Identifier -- [HL + byte] Description
[Description example] MOV A, [HL + 10H]; When setting byte to 10H
Instruction code 1 0 1 0 1 1 1 0
0
0
0
1
0
0
0
0
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5.4.9 Based indexed addressing [Function] The B or C register contents specified in an instruction are added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. The HL, B, and C registers to be accessed are registers in the register bank specified with the register bank select flag (RBS0 and RBS1). The contents of the B or C register as a positive number are expanded to 16 bits to be added. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format]
Identifier -- Description [HL + B], [HL + C]
[Description example] In the case of MOV A, [HL + B]
Instruction code 1 0 1 0 1 0 1 1
5.4.10 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and RETURN
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instructions are executed or the register is saved/reset upon generation of an interrupt request. Stack addressing enables to address the internal high-speed RAM area only. [Description example] In the case of PUSH DE
Instruction code 1 0 1 1 0 1 0 1
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PORT FUNCTIONS
6.1 Port Functions The PD78014 and 78014Y Subseries each incorporate two input ports and fifty-one input/output ports. Figure 6-1 shows the port types. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations. Besides port functions, the ports can also serve as on-chip hardware input/output pins.
Figure 6-1. Port Types
P30
P00 Port 0
Port 3
P04 P10 P37
Port 4
8
P40 to P47 P50 P17
Port 1
Port 5
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P20
P57 P60 P27 Port 6
Port 2
P67
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Table 6-1. Port Functions (PD78014 Subseries) (1/2)
Pin Name Function Alternate Function P00 P01 P02 P03 P04 P10 to P17 Port 1. 8-bit input/output port. Input/output specifiable bit-wise. If used as an input port, on-chip pull-up resistor is enabled by software. P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32
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Port 0. 5-bit input/output port.
Input only. Input/output specifiable bit-wise. If used as an input port, on-chip pull-up resistor can be enabled by software. Input only.
INTP0/TI0 INTP1 INTP2 INTP3 XT1 ANI0 to ANI7
Port 2. 8-bit input/output port. Input/output specifiable bit-wise. If used as an input port, on-chip pull-up resistor is enabled by software.
SI1 SO1 SCK1 STB BUSY SI0/SB0 SO0/SB1 SCK0
Port 3. 8-bit input/output port. Input/output specifiable bit-wise. If used as an input port, on-chip pull-up resistor is enabled by software.
TO0 TO1 TO2 TI1 TI2 PCL BUZ --
P33 P34 P35 P36 P37 P40 to P47
Port 4. 8-bit input/output port. Input/output can be specified in 8-bit units. When used as an input port, on-chip pull-up resistor is enabled by software. Test input flag (KRIF) is set to 1 by falling edge detection.
AD0 to AD7
P50 to P57
Port 5. 8-bit input/output port. LED can be driven directly. Input/output specifiable bit-wise. When used as an input port, on-chip pull-up resistor is enabled by software.
A8 to A15
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Table 6-1. Port Functions (PD78014 Subseries) (2/2)
Pin Name Function Alternate Function P60 P61 P62 P63 P64 P65 P66 P67 Port 6. 8-bit input/output port. Input/output specifiable bit-wise. N-ch open-drain input/output port. On-chip pull-up resistor can be specified by mask option only for mask ROM versions. LED can be driven directly. When used as an input port, on-chip pull-up RD resistor is enabled by software. WR WAIT ASTB --
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Table 6-2. Port Functions (PD78014Y Subseries) (1/2)
Pin Name Function Alternate Function P00 P01 P02 P03 P04 P10 to P17 Port 1. 8-bit input/output port. Input/output specifiable bit-wise. If used as an input port, on-chip pull-up resistor is enabled by software. P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32
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Port 0. 5-bit input/output port.
Input only. Input/output specifiable bit-wise. If used as an input port, on-chip pull-up resistor can be enabled by software. Input only.
INTP0/TI0 INTP1 INTP2 INTP3 XT1 ANI0 to ANI7
Port 2. 8-bit input/output port. Input/output specifiable bit-wise. If used as an input port, on-chip pull-up resistor is enabled by software.
SI1 SO1 SCK1 STB BUSY SI0/SB0/SDA0 SO0/SB1/SDA1 SCK0/SCL
Port 3. 8-bit input/output port. Input/output specifiable bit-wise. If used as an input port, on-chip pull-up resistor is enabled by software.
TO0 TO1 TO2 TI1 TI2 PCL BUZ --
P33 P34 P35 P36 P37 P40 to P47
Port 4. 8-bit input/output port. Input/output can be specified in 8-bit units. When used as an input port, on-chip pull-up resistor is enabled by software. Test input flag (KRIF) is set to 1 by falling edge detection.
AD0 to AD7
P50 to P57
Port 5. 8-bit input/output port. LED can be driven directly. Input/output specifiable bit-wise. When used as an input port, on-chip pull-up resistor is enabled by software.
A8 to A15
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Table 6-2. Port Functions (PD78014Y Subseries) (2/2)
Pin Name Function Alternate Function P60 P61 P62 P63 P64 P65 P66 P67 Port 6. 8-bit input/output port. Input/output specifiable bit-wise. N-ch open-drain input/output port. On-chip pull-up resistor can be specified by mask option only for mask ROM versions. LED can be driven directly. When used as an input port, on-chip pull-up RD resistor is enabled by software. WR WAIT ASTB --
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6.2 Port Block Diagram A port consists of the following hardware.
Table 6-3. Port Block Diagram
Item Control register Port mode register Pull-up resistor option register Memory expansion mode register Key return mode register Port Pull-up resistor Configuration (PMm: m = 0, 1, 2, 3, 5, 6) (PUO) (MM)Note (KRM)
Total: 53 ports (2 inputs, 51 inputs/outputs) * Mask ROM versions Total: 51 (software control: 47, mask option control: 4) * PD78P014, 78P014Y Total: 47
Note
Memory expansion mode registers specify input/output of Port 4.
6.2.1 Port 0 Port 0 is a 5-bit input/output port with output latch. P01 to P03 pins can be set to the input mode/output mode bit-wise with the port mode register 0 (PM0). P00 and P04 pins are input-only ports. When P01 to P03 pins are used as input ports, a pull-up resistor can be connected to them in 3-bit units with an on-chip pull-up resistor option register (PUO). Alternate functions include external interrupt request input, external count clock input to the timer and crystal
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connection for subsystem clock oscillation. RESET input sets port 0 to input mode. Figures 6-2 to 6-4 show block diagrams of port 0. Caution Because port 0 is also used for external interrupt request input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. Thus, when the output mode is used, set the interrupt mask flag to 1.
Figure 6-2. P00 Block Diagram
RD
Internal Bus
P00/INTP0/TI0 Edge detection
RD
: Port 0 read signal
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Figure 6-3. P01 to P03 Block Diagrams
VDD WRPUO
PUO0 RD
P-ch
Selector
Internal Bus
WRPORT Output Latch (P01 to P03) P01/INTP1 to P03/INTP3
WRPM
PM01 to PM03
PUO : Pull-up resistor option register PM RD
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: Port mode register : Port 0 read signal
WR : Port 0 write signal
Figure 6-4. P04 Block Diagram
RD
Internal Bus
P04/XT1
RD
: Port 0 read signal
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6.2.2 Port 1 Port 1 is an 8-bit input/output port with output latch. P10 to P17 pins can be set to the input mode/output mode bit-wise with a port mode register 1 (PM1). When P10 to P17 pins are used as input ports, an on-chip pull-up resistor can be connected to them in 8-bit units with a pull-up resistor option register (PUO). Alternate functions include an A/D converter analog input. RESET input sets port 1 to input mode. Figure 6-5 shows a block diagram of port 1. Caution On-chip pull-up resistor cannot be used for pins used as A/D converter analog input.
Figure 6-5. P10 to P17 Block Diagrams
VDD WRPUO
PUO1 RD
P-ch
Selector
Internal Bus
WRPORT Output Latch (P10 to P17) P10/ANI0 to P17/ANI7
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WRPM
PM10 to PM17
PUO : Pull-up resistor option register PM RD : Port mode register : Port 1 read signal
WR : Port 1 write signal
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6.2.3 Port 2 (PD78014 Subseries) Port 2 is an 8-bit input/output port with output latch. P20 to P27 pins can be set to the input mode/output mode bit-wise with the port mode register 2 (PM2). When P20 to P27 pins are used as input ports, a pull-up resistor can be connected to them in 8-bit units with an on-chip pull-up resistor option register (PUO). Alternate functions include serial interface data input/output, clock input/output, automatic transmit/receive busy input, and strobe output. RESET input sets port 2 to input mode. Figures 6-6 and 6-7 show a block diagram of port 2. Cautions 1. If used as alternate function pin, set the input/output latch according to the functions. Refer to Figure 15-5 Serial Operating Mode Register 0 Format and Figure 17-3 Serial Operating Mode Register 1 Format for setting. 2. When the status of pins is read in the SBI mode, set PM2n of the PM2 to 1 (n = 5 or 6) (refer to 15.4.3 SBI mode operation (10) Distinction method of slave busy state).
Figure 6-6. P20, P21, P23 to P26 Block Diagrams (PD78014 Subseries)
VDD WRPUO
PUO2 RD
P-ch
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Selector
Internal Bus
WRPORT
Output Latch (P20, P21, P23 to P26)
P20/SI1, P21/SO1, P23/STB, P24/BUSY, P25/SI0/SB0, P26/SO0/SB1
WRPM PM20, PM21, PM23 to PM26
Alternate Function
PUO : Pull-up resistor option register PM RD : Port mode register : Port 2 read signal
WR : Port 2 write signal
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Figure 6-7. P22 and P27 Block Diagrams (PD78014 Subseries)
VDD WRPUO
PUO2 RD
P-ch
Selector Internal Bus WRPORT Output Latch (P22, P27)
P22/SCK1, P27/SCK0
WRPM
PM22, PM27 Alternate Function
PUO : Pull-up resistor option register PM
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: Port mode register : Port 2 read signal
RD
WR : Port 2 write signal
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6.2.4 Port 2 (PD78014Y Subseries) Port 2 is an 8-bit input/output port with output latch. P20 to P27 pins can be set to the input mode/output mode bit-wise with the port mode register 2 (PM2). When P20 to P27 pins are used as input ports, an on-chip pull-up resistor can be connected to them in 8-bit units with a pull-up resistor option register (PUO). Alternate functions include serial interface data input/output, clock input/output, automatic transmit/receive busy input, and strobe output. RESET input sets port 2 to input mode. Figures 6-8 and 6-9 show a block diagram of port 2. Cautions 1. If used as alternate function pin, set the input/output latch according to the functions. Refer to Figure 16-6 Serial Operating Mode Register 0 Format and Figure 17-3 Serial Operating Mode Register 1 Format for setting. 2. When the status of pins is read in the SBI mode, set PM2n of the PM2 to 1 (n = 5 or 6) (refer to 16.4.3 SBI mode operation (10) Distinction method of slave busy state).
Figure 6-8. P20, P21, P23 to P26 Block Diagrams (PD78014Y Subseries)
VDD WRPUO
PUO2 RD
P-ch
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Selector
Internal Bus
WRPORT
Output Latch (P20, P21, P23 to P26)
WRPM PM20, PM21, PM23 to PM26
P20/SI1, P21/SO1, P23/STB, P24/BUSY, P25/SI0/SB0/ SDA0, P26/SO0/SB1/ SDA1
Alternate Function
PUO : Pull-up resistor option register PM RD : Port mode register : Port 2 read signal
WR : Port 2 write signal
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Figure 6-9. P22 and P27 Block Diagrams (PD78014Y Subseries)
VDD WRPUO
PUO2 RD
P-ch
Selector
Internal Bus
WRPORT Output Latch (P22, P27)
P22/SCK1, P27/SCK0/ SCL
WRPM
PM22, PM27 Alternate Function
PUO : Pull-up resistor option register
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PM RD
: Port mode register : Port 2 read signal
WR : Port 2 write signal
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6.2.5 Port 3 Port 3 is an 8-bit input/output port with output latch. P30 to P37 pins can be set to the input mode/output mode bit-wise with the port mode register (PM3). When P30 to P37 pins are used as input ports, an on-chip pull-up resistor can be connected to them in 8-bit units with a pull-up resistor option register (PUO). Alternate functions include timer input/output, clock output and buzzer output. RESET input sets port 3 to input mode. Figure 6-10 shows a block diagram of port 3.
Figure 6-10. P30 to P37 Block Diagrams
VDD
WRPUO PUO3 RD P-ch
Selector
Internal Bus
WRPORT Output Latch (P30 to P37)
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WRPM PM30 to PM37 Alternate Function
P30/TO0, P31/TO1, P32/TO2, P33/TI1, P34/TI2, P35/PCL, P36/BUZ, P37
PUO : Pull-up resistor option register PM RD : Port mode register : Port 3 read signal
WR : Port 3 write signal
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6.2.6 Port 4 Port 4 is an 8-bit input/output port with output latch. P40 to P47 pins can be set to the input mode/output mode in 8-bit units with the memory expansion mode register (MM). When P40 to P47 pins are used as input ports, a pullup resistor can be connected to them in 8-bit units with an on-chip pull-up resistor option register (PUO). Test input flag (KRIF) is set to 1 by falling edge detection. Alternate functions include address/data bus in external memory expansion mode. RESET input sets port 4 to input mode. Figure 6-11 shows a block diagram of port 4. Figure 6-12 shows a block diagram of the falling edge detector.
Figure 6-11. P40 to P47 Block Diagrams
VDD WRPUO PUO4 RD P-ch
Selector
Internal Bus
WRPORT Output Latch (P40 to P47) P40/AD0 to P47/AD7
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WRMM MM
PUO : Pull-up resistor option register MM : Memory expansion mode register RD : Port 4 read signal WR : Port 4 write signal
Figure 6-12. Block Diagram of Falling Edge Detector
P40 P41 P42 P43 P44 P45 P46 P47 KRMK standby release signal Falling Edge Detector KRIF set signal
KRIF
: Test input flag
KRMK : Test mask flag
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6.2.7 Port 5 Port 5 is an 8-bit input/output port with output latch. P50 to P57 pins can be set to the input mode/output mode bit-wise with the port mode register 5 (PM5). When P50 to P57 pins are used as input ports, an on-chip pull-up resistor can be connected to them in 8-bit units with a pull-up resistor option register (PUO). Port 5 can drive LEDs directly. Alternate functions include address bus in external memory expansion mode. RESET input sets port 5 to input mode. Figure 6-13 shows a block diagram of port 5.
Figure 6-13. P50 to P57 Block Diagrams
VDD WRPUO PUO5 RD P-ch
Selector
Internal Bus
WRPORT Output Latch (P50 to P57) P50/A8 to P57/A15
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WRPM PM50 to PM57
PUO : Pull-up resistor option register PM RD : Port mode register : Port 5 read signal
WR : Port 5 write signal
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6.2.8 Port 6 Port 6 is an 8-bit input/output port with output latches. P60 to P67 pins can be set to either input mode or output mode in 1-bit units with port mode register 6 (PM6). This port has the following functions related to the pull-up resistor. These functions deffer depending on the upper 4 bits or the lower 4 bits of the port, and mask ROM versions or PROM versions.
Table 6-4. Pull-Up Resistors for Port 6
Upper 4 bits (P64 to P67 pins) Mask version The on-chip pull-up resistor can be connected to the P64 to P67 pins in 4-bit units with PU06. PROM version PUO6: Bit 6 of the pull-up resistor option register Lower 4 bits (P60 to P63 pins) The pull-up resistor can be connected bit-wise by mask option. The pull-up resistor is not contained.
P60 to P63 pins can drive LEDs directly. The alternate function of the P60 to P63 pins is control signal output in external memory expansion mode. RESET input sets port 6 to input mode. Tables 6-14 and 6-15 show the block diagrams of port 6. Cautions 1. 2. When external wait is not used in external memory expansion mode, P66 can be used as an input/output port. The value of low-level input leakage current at the P60 to P63 pins depends on the following conditions. [Mask ROM version]
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* *
When the pull-up resistor is contained: always -3 A (max.) When the pull-up resistor is not contained: * * Within 3 clocks after a read is executed to Port 6 (P6) or Port mode register 6 (PM6) (when no wait cycles are inserted): -200 A (max.) In other cases: -3 A (max.)
[PROM version] * * Within 3 clocks after a read is executed to Port 6 (P6) or Port mode register 6 (PM6) (when no wait cycles are inserted): -200 A (max.) In other cases: -3 A (max.)
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Figure 6-14. P60 to P63 Block Diagrams
VDD RD Mask Option resistors Mask ROM versions only PD78P014 and 78P014Y have no pull-up resistor. Selector Internal Bus WRPORT Output Latch (P60 to P63) P60 to P63
WRPM PM60 to PM63
PM RD
: Port mode register : Port 6 read signal
WR : Port 6 write signal
Figure 6-15. P64 to P67 Block Diagrams
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VDD WRPUO PUO6 RD P-ch
Selector Internal Bus WRPORT Output Latch (P64 to P67) P64/RD, P65/WR, P66/WAIT, P67/ASTB
WRPM PM64 to PM67
PUO : Pull-up resistor option register PM RD : Port mode register : Port 6 read signal
WR : Port 6 write signal
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6.3 Port Function Control Registers The following four types of registers control the ports. * Port mode registers (PM0, PM1, PM2, PM3, PM5, PM6) * Pull-up resistor option register (PUO) * Memory expansion mode register (MM) * Key return mode register (KRM) (1) Port mode registers (PM0, PM1, PM2, PM3, PM5, PM6) These registers are used to set port input/output bit-wise. PM0, PM1, PM2, PM3, PM5, and PM6 are independently set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM0 to 1FH and other registers to FFH. When a port pin is used as its alternate function pin, set the port mode register and the output latch according to Table 6-5. Cautions 1. 2. 3. P00 and P04 pins are input-only pins. Input/output of P40 to P47 pins are specifiable with a memory expansion mode register (MM). As port 0 is also used for external interrupt request input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. When the output mode is used, therefore, the interrupt mask flag should be set to 1 beforehand.
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Table 6-5. Port Mode Register and Output Latch Setting when Alternate Function is Used
Pin Name Alternate Function Function Name P00 INTP0 TI0 P01 to P03 P04
Note 1
PMxx
Pxx
Pin Name
Alternate Function Function Name Input/ Output Input/ Output
PMxx
Pxx
Input/ Output Input Input 1 (defined) None 1 (defined) None 1 x x 0 x 0 0 P50 to P57 P64 P65 P66 P67 P40 to P47
AD0 to AD7
xNote 2 xNote 2 xNote 2 xNote 2 xNote 2 xNote 2
INTP1 to INTP3 Input XT1 Input Input
A8 to A15 RD WR WAIT ASTB
Output Output Output Input Output
1 (defined) None 1
P10 to P17Note 1 ANI0 to ANI7 P30 to P32 P33, P34 P35 P36 TO0 to TO2 TI1, TI2 PCL BUZ
Output 0 Input 1
Output 0 Output 0
Notes 1. Read data will be undefined if the read instruction is executed for the port when used as alternate function pin. 2. When pins P40 to P47, P50 to P57 and P64 to P67 are used as alternate function pins, set the functions with a memory expansion mode register (MM). Cautions 1. 2.
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When external wait is not used in memory expansion mode, P66 pin can be used as an input/ output port. When Port 2 is used as serial interface pin, input/output and the output latch should be set according to functions. For setting, refer to Figure 15-5 Serial Operating Mode Register 0 Format, Figure 16-6 Serial Operating Mode Register 0 Format, and Figure 17-3 Serial Operating Mode Register 1 Format.
Remark x PMxx Pxx
: don't care (no setting required) : Port mode register : Port output latch
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Figure 6-16. Port Mode Register Format
Symbol PM0
7 0
6 0
5 0
4 1
3 PM03
2 PM02
1 PM01
0 1
Address FF20H
When Reset 1FH
R/W R/W
PM1
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
FF21H
FFH
R/W
PM2
PM27
PM26
PM25
PM24
PM23
PM22
PM21
PM20
FF22H
FFH
R/W
PM3
PM37
PM36
PM35
PM34
PM33
PM32
PM31
PM30
FF23H
FFH
R/W
PM5
PM57
PM56
PM55
PM54
PM53
PM52
PM51
PM50
FF25H
FFH
R/W
PM6
PM67
PM66
PM65
PM64
PM63
PM62
PM61
PM60
FF26H
FFH
R/W
PMmn
Pmn Pin Input/Output Mode Select (m = 0, 1, 2, 3, 5, 6: n = 0 to 7)
0 1
Output mode (output buffer ON) Input mode (output buffer OFF)
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(2) Pull-up resistor option register (PUO) This register is used to set whether to use an on-chip pull-up resistor at each port or not. An on-chip pull-up resistor is internally used only for the bits that are set to the input mode at a port where pull-up resistor use has been specified with PUO. No on-chip pull-up resistors can be used to the bits set to the output mode or to the bits used as an analog input pin, irrespective of PUO setting. PUO is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Cautions 1. 2. 3. P00 and P04 pins do not incorporate a pull-up resistor. When port 1, port 4, port 5, or P64 to P67 is used as an alternate function pin, an on-chip pullup resistor cannot be connected even if 1 is set in PUOm (m = 1, 4 to 6). For P60 to P63 pins, only mask ROM versions can contain pull-up resistors by mask option.
Figure 6-17. Pull-Up Resistor Option Register Format
Symbol PUO
7 0
<6>
<5>
<4> PUO4
<3> PUO3
<2> PUO2
<1> PUO1
<0> PUO0
Address FFF7H
When Reset 00H
R/W R/W
PUO6 PUO5
PUOm
Pm On-chip Pull-up Resistor (m = 0, 1, 2, 3, 4, 5, 6)
0
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On-chip pull-up resistor not used On-chip pull-up resistor used
1
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(3) Memory expansion mode register (MM) The registers are used to set port 4 input/output. MM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets MM to 10H.
Figure 6-18. Memory Expansion Mode Register Format
Symbol MM 7 0 6 0 5 PW1 4 PW0 3 0 2 MM2 1 MM1 0 MM0 Address FFF8H When Reset 10H R/W R/W
MM2
MM1
MM0
Single-chip/Memory
P40 to P47, P50 to P57, P64 to P67 Pins Condition P54, P55 P56, P57 P64 to P67
Expansion Mode Selection P40 to P47 P50 to P53 0 0 0 0 0 1 0 1 1 Memory expansion 1 0 0 mode 256 bytes mode 4 Kbytes mode 1 0 1 16 Kbytes mode 1 1 1 Full-address modeNote Other than above
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Single-chip mode
Port Input mode Output AD0 to AD7
Port mode
Port mode
P64 = RD P65 = WR
A8 to A11
Port mode
P66 = WAIT P67 = ASTB
A12, A13
Port mode
A14, A15
Setting prohibited
PW1 0 0 1 1
PW0 0 1 0 1
Wait Control No wait With wait (1-wait state insertion) Setting prohibited Wait control with an external wait pin
Note
Full-address mode is the mode that can execute external expansion to all the areas other than internal ROM, RAM, SFR areas and the reserved areas in 64 K address space.
Remarks 1. P60 to P63 pins enter the port mode regardless of the single-chip mode or memory expansion mode. 2. Besides it is used to set port 4 input/output, MM has functions to set the number of waits and external expansion area.
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(4) Key return mode register (KRM) The registers are used to set standby mode release enable/disable with the key return signal (falling edge detection of port 4). KRM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets KRM to 02H.
Figure 6-19. Key Return Mode Register Format
Symbol KRM 7 0 6 0 5 0 4 0 3 0 2 0 <1> KRMK <0> KRIF Address FFF6H When Reset 02H R/W R/W
KRIF 0 1
Key Return Signal Detection Flag Undetected Detected (falling edge detection of port 4)
KRMK 0 1
Standby Mode Control with Key Return Signal Standby mode release enable Standby mode release disable
Caution
When falling edge detection is used in port 4, be sure to clear KRIF to 0 (KRIF cannot be cleared to 0 automatically).
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6.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 6.4.1 Writing to input/output port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again. (2) Input mode A value is written to the output latch by a transfer instruction, but since the output buffer is OFF, the pin status does not change. Once data is written to the output latch, it is retained until data is written to the output latch again. Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are also undefined in addition to the manipulated bit.
6.4.2 Reading from input/output port
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(1) Output mode The output latch contents are read by a transfer instruction. The output latch contents do not change. (2) Input mode The pin status is read by a transfer instruction. The output latch contents do not change.
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6.4.3 Operations on input/output port (1) Output mode An operation is performed on the output latch contents, and the result is written to the output latch. The output latch contents are output from the pins. Once data is written to the output latch, it is retained until data is written to the output latch again. (2) Input mode The output latch contents are undefined, but since the output buffer is OFF, the pin status does not change. Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are also undefined in addition to the manipulated bit.
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6.5 Mask Options Mask ROM versions can contain a pull-up resistor in P60 to P63 pins bit-wise with the mask option. The PD78P014 and 78P014Y have no mask option and do not contain a pull-up resistor for P60 to P63 pins.
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CLOCK GENERATOR
7.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are available. (1) Main system clock oscillator Oscillates at frequencies of 1.0 to 10.0 MHz. Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register (PPC). (2) Subsystem clock oscillator Oscillates at a frequency of 32.768 kHz. Oscillation cannot be stopped. If the subsystem clock oscillator is not used, the on-chip feedback resistor can be set to disable by the processor clock control register (PCC). This enables to decrease power consumption in the STOP mode. 7.2 Clock Generator Configuration The clock generator consists of the following hardware.
Table 7-1. Clock Generator Configuration
Item
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Configuration Processor clock control register (PCC) Main system clock oscillator Subsystem clock oscillator
Control register Oscillator
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Selector
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FRC XT1/P04 XT2 Subsystem clock oscillator circuit fXT X1 X2 Main system clock oscillator circuit fX fX 2 fX 22 STOP
Figure 7-1. Clock Generator Block Diagram
Watch timer, clock output function
Prescaler
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Prescaler fX 23 fX 24 Standby control circuit To INTP0 sampling clock Wait control circuit
Clock to peripheral hardware
CLOCK GENERATOR
CPU clock
3
MCC
FRC
CLS
CSS
PCC2
PCC1 PCC0
Processor clock control register
Internal bus
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7.3 Clock Generator Control Register The clock generator is controlled by the processor clock control register (PCC). The PCC sets CPU clock selection, the ratio of division, main system clock oscillator operation/stop and subsystem clock oscillator on-chip feedback resistor enable/disable. The PCC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets the PCC to 04H.
Figure 7-2. Feedback Resistor of Subsystem Clock
FRC P-ch Feedback resistor
XT1
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XT2
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Figure 7-3. Processor Clock Control Register Format
Symbol PCC <7> MCC <6> FRC <5> CLS <4> CSS 3 0 2 PCC2 1 PCC1 0 PCC0 R/W Address FFFBH When Reset 04H R/W R/WNote 1
CSS
PCC2
PCC1
PCC0
CPU Clock (fCPU) selection
0
0 0 0 0 1
0 0 1 1 0 0 0 1 1 0
0 1 0 1 0 0 1 0 1 0
fX fX/2 fX/22 fX/23 fX/24 fXT
1
0 0 0 0 1
Other than above R
Setting prohibited
CLS 0 1
CPU Clock Status Main system clock Subsystem clock
R/W
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FRC 0 1
Subsystem Clock Feedback Resistor Selection On-chip feedback resistor used On-chip feedback resistor not used
R/W
MCC 0 1
Main System Clock Oscillation ControlNote 2 Oscillation possible Oscillation stopped
Notes 1. Bit 5 is Read Only. 2. When the CPU is operating on the subsystem clock, MCC should be used to stop the main system clock oscillation. A STOP instruction should not be used. Caution Remarks Bit 3 must be set to 0. 1. 2. fX fXT : Main system clock oscillation frequency : Subsystem clock oscillation frequency
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The fastest instruction of the PD78014, 78014Y Subseries is executed by the CPU clock 4 clock. The relationship between the CPU clock (fCPU) and minimum instruction execution time is as shown in Table 7-2.
Table 7-2. Relationship between CPU Clock and Minimum Instruction Execution Time
CPU Clock (fCPU) fX fX/2 fX/2
2
Minimum Instruction Execution Time: 4/fCPU 0.4 s 0.8 s 1.6 s 3.2 s 6.4 s 122 s
fX/23 fX/2 fXT
4
fX = 10.0 MHz, fXT = 32.768 kHz fX : Main system clock oscillation frequency fXT : Subsystem clock oscillation frequency
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7.4 System Clock Oscillator 7.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 10.0 MHz) connected to the X1 and X2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the X1 pin and its inverted signal to the X2 pin. Figure 7-4 shows an external circuit of the main system clock oscillator.
Figure 7-4. External Circuit of Main System Clock Oscillator
(a) Crystal or ceramic oscillation (b) External clock
X2
X2
X1 IC Crystal or Ceramic resonator
External clock
X1
PD74HCU04
Caution
The STOP mode cannot be set while an external clock is being input. This is because the X1 pin is short-circuited to VSS in the STOP mode.
7.4.2 Subsystem clock oscillator
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The subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 External clocks can be input to the subsystem clock oscillator. In this case, input a clock signal to the XT1 pin
and XT2 pins. and its inverted signal to the XT2 pin. Figure 7-5 shows an external circuit of the subsystem clock oscillator.
Figure 7-5. External Circuit of Subsystem Clock Oscillator
(a) Crystal oscillation
IC XT2 External clock
(b) External clock
XT2
32.768 kHz
XT1
XT1
PD74HCU04
Cautions are shown on the next page.
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Cautions 1.
When using a main system clock oscillator and a subsystem clock oscillator, wire the portion enclosed in the dotted line areas in Figures 7-4 and 7-5 as follows to avoid adverse influence on the wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring over the other signal lines. Do not route the wiring in the vicinity of lines through which a high fluctuating current flows. * Always keep the ground point of the capacitor of the oscillator circuit at the same potential as VSS. Do not connect the power source pattern through which a high current flows. * Do not extract signals from the oscillator. Take special note of the fact that the subsystem clock oscillator is a circuit with low-level amplification so that current consumption is maintained at low levels. Figure 7-6 shows examples of resonator having bad connection.
Figure 7-6. Examples of Resonator with Bad Connection (1/2)
(a) Long wiring of connected circuit (b) Crossed signal lines
PORTn (n = 0 to 6)
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X2
X1
IC
X2
X1
IC
Remark
When using a subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Further, insert resistors in series on the side of XT2.
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Figure 7-6. Examples of Resonator with Bad Connection (2/2)
(c) High fluctuating current close to signal lines (d) Current flowing through ground line of oscillator circuit (potentials at points A, B, and C change.)
VDD
Pnm X2 High current X1 IC X2 X1 IC
A
B High current
C
(e) Signal extracted
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X2
X1
IC
Remark
When using a subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Further, insert resistors in series on the side of XT2.
Cautions 2.
When XT2 and X1 are wired parallel, X1 crosstalk noise may affect XT2 and cause an error. To prevent that from happening, it is recommended to connect the IC pin between XT2 and X1 to VSS as well as not wire XT2 and X1 in parallel.
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7.4.3 Divider The divider divides the main system clock oscillator output (fX) and generates various clocks. 7.4.4 When no subsystem clocks are used If it is not necessary to use subsystem clocks for low power consumption operations and watch operations, connect the XT1 and XT2 pins as follows. XT1: Connect to VDD or VSS XT2: Open In this state, however, some current may leak via the on-chip feedback resistor of the subsystem clock oscillator when the main system clock stops. To prevent that from happening, the above on-chip feedback resistor (PCC) can be removed with bit 6 (FRC) of the processor clock control register (PCC). In this case also, connect the XT1 and XT2 pins as described above.
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7.5 Clock Generator Operations The clock generator generates the following types of clocks and controls the CPU operating mode including the standby mode. * Main system clock fX * Subsystem clock fXT * CPU clock fCPU * Clock to peripheral hardware The function and operation of the clock generator circuit are determined by the processor clock control register (PCC) as follows: (a) Upon generation of the RESET signal, the lowest speed mode of the main system clock (6.4 s when operated at 10.0 MHz) is selected (PCC = 04H). Main system clock oscillation stops while low level is applied to the RESET pin. (b) With the main system clock selected, one of the five (0.4 s, 0.8 s, 1.6 s, 3.2 s and 6.4 s: when operated at 10.0 MHz) CPU clock stages can be selected by setting the PCC. (c) With the main system clock selected, two standby modes, the STOP and HALT modes, are available. With the subsystem clock unused, the current consumption in STOP mode can be further decreased by disabling the subsystem clock feedback resistor with PCC bit 6 (FRC).
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(d) The PCC can be used to select the subsystem clock and to operate the system with low current consumption (122 s at 32.768 kHz operation).
(e) With the subsystem clock selected, main system clock oscillation can be stopped with the PCC. The HALT mode can be used. However, the STOP mode cannot be used. (Subsystem clock oscillation cannot be stopped.) (f) The main system clock is divided and supplied to the peripheral hardware. The subsystem clock is supplied to the watch timer and clock output functions only. Thus, the watch function and the clock output function can also be continued in the standby state. However, since all other peripheral hardware operate with the main system clock, the peripheral hardware also stops if the main system clock is stopped (except external input clock operation).
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7.5.1 Main system clock operations When operated with the main system clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 0), the following operations are carried out by PCC setting. (a) Because the operation guarantee instruction execution speed depends on the power supply voltage, the minimum instruction execution time can be changed by bits 0 to 2 (PCC0 to PCC2) of the PCC. (b) If bit 7 (MCC) of the PCC is set to 1 when operated with the main system clock, the main system clock oscillation does not stop. When bit 4 (CSS) of the PCC is set to 1 and the operation is switched to subsystem clock operation (CLS = 1) after that, the main system clock oscillation stops (see Figure 7-7).
Figure 7-7. Main System Clock Stop Function (1/2) (a) Operation when MCC is set after setting CSS with main system clock operation
MCC
CSS
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CLS
Main System Clock Oscillation
Subsystem Clock Oscillation
CPU Clock
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Figure 7-7. Main System Clock Stop Function (2/2) (b) Operation when MCC is set with main system clock operation
MCC CSS CLS "L" "L" Oscillation does not stop. Main System Clock Oscillation
Subsystem Clock Oscillation
CPU Clock
(c) Operation when CSS is set after setting MCC with main system clock operation
MCC
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CSS
CLS
Main System Clock Oscillation
Subsystem Clock Oscillation
CPU Clock
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7.5.2 Subsystem clock operations When operated with the subsystem clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 1), the following operations are carried out. (a) The minimum instruction execution time remains constant (122 s when operated at 32.768 kHz) irrespective of bits 0 to 2 (PCC0 to PCC2) of the PCC. (b) Watchdog timer counting stops. Caution Do not execute the STOP instruction while the subsystem clock is in operation.
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7.6 Changing System Clock and CPU Clock Settings 7.6.1 Time required for switchover between system clock and CPU clock The system clock and CPU clock can be switched over by means of bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC). The actual switchover operation is not performed directly after writing to the PCC, but operation continues on the pre-switchover clock for several instructions (see Table 7-3). Determination as to whether the system is operating on the main system clock or the subsystem clock is performed by bit 5 (CLS) of the PCC register.
Table 7-3. Maximum Time Required for CPU Clock Switchover
Set Values before Switchover CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 x x x Set Values after Switchover
16 instructions
16 instructions
16 instructions
16 instructions
fX/4fXT instructions (77 instructions)
0
0
1
8 instructions
8 instructions
8 instructions
8 instructions
fX/8fXT instructions (39 instructions)
0
1
0
4 instructions
4 instructions
4 instructions
4 instructions
fX/16fXT instructions (20 instructions)
0
1
1
2 instructions
2 instructions
2 instructions
2 instructions
fX/32fXT instructions (10 instructions)
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1
0
0
1 instruction
1 instruction
1 instruction
1 instruction
fX/64fXT instructions (5 instructions)
1
x
x
x
1 instruction
1 instruction
1 instruction
1 instruction
1 instruction
Caution
Selection of the CPU clock cycle dividing factor (PCC0 to PCC2) and switchover from the main system clock to the subsystem clock (changing CSS from 0 to 1) should not be performed simultaneously. Simultaneous setting is possible, however, for selection of the CPU clock cycle dividing factor (PCC0 to PCC2) and switchover from the subsystem clock to the main system clock (changing CSS from 1 to 0).
Remarks
1. 2.
One instruction is the minimum instruction execution time with the pre-switchover CPU clock. Values in parentheses apply to operation with fX = 10.0 MHz or fXT = 32.768 kHz.
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7.6.2 System clock and CPU clock switching procedure This section describes switching procedure between system clock and CPU clock.
Figure 7-8. System Clock and CPU Clock Switching
VDD
RESET
Interrupt Request Signal
System Clock CPU Clock
fX
fX
fXT Subsystem Clock Operation
fX High-Speed Operation
Minimum Maximum Speed Operation Speed Operation Wait (26.2 ms : @ 10.0 MHz) Internal Reset Operation
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(1)The CPU is reset by setting the RESET signal to low level after power-on. After that, when reset is released by setting the RESET signal to high level, the main system clock starts oscillation. At this time, the oscillation stabilization time (218/fX) is secured automatically. After that, the CPU starts executing the instruction at the minimum speed of the main system clock (6.4 s when operated at 10.0 MHz). (2)After the lapse of a sufficient time for the VDD voltage to increase to enable operation at maximum speed, the processor clock control register (PCC) is rewritten and maximum-speed operation is carried out. (3)Upon detection of a decrease of the VDD voltage due to an interrupt request signal, the main system clock is switched to the subsystem clock (which must be in an oscillation stabilization state). (4)Upon detection of VDD voltage reset due to an interrupt request signal, 0 is set to PCC bit 7 (MCC) and oscillation of the main system clock is started. After the lapse of time required for stabilization of oscillation, the PCC is rewritten and maximum-speed operation is resumed. Caution When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock.
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[MEMO]
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CHAPTER 8
16-BIT TIMER/EVENT COUNTER
8.1 Outline of On-chip Timer in PD78014, 78014Y Subseries This section describes the 16-bit timer/event counter. First an outline of the built-in timer in the PD78014 and 78014Y Subseries and the related items are shown in the following. (1) 16-bit timer/event counter (TM0) The TM0 can be used for an interval timer, PWM output, pulse width measurement (infrared ray remote control receive function), external event counter or square wave output of any frequency. (2) 8-bit timer/event counters (TM1 and TM2) TM1 and TM2 can be used to serve as an interval timer and an external event counter and to output square waves with any selected frequency. Two 8-bit timer/event counters can be used as one 16-bit timer/event counter (See CHAPTER 9 8-BIT TIMER/EVENT COUNTER). (3) Watch timer (TM3) This timer can set a flag every 0.5 sec. and simultaneously generates interrupt requests at the preset time intervals (See CHAPTER 10 WATCH TIMER). (4) Watchdog timer (WDTM) WDTM can perform the watchdog timer function or generate non-maskable interrupt requests, maskable interrupt requests and RESET at the preset time intervals (See CHAPTER 11 WATCHDOG TIMER).
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(5) Clock output control circuit This circuit supplies other devices with the divided main system clock and the subsystem clock (See CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT). (6) Buzzer output control circuit This circuit outputs the buzzer frequency obtained by dividing the main system clock (See CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT).
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Table 8-1. Timer/Event Counter Operation
16-Bit Timer/ Event Counter Operation mode Function Interval timer External event counter Timer output PWM output Pulse width measurement Square-wave output Interrupt request Test input -- -- -- -- -- 1 channel 8-Bit Timer/ Event Counter 2 channels 1 channel -- -- -- -- --
Note 1
Watch Timer
Watchdog Timer 1 channelNote 2 -- -- -- -- --
Notes 1. Watch timer can perform both watch timer and interval timer functions at the same time. 2. Watchdog timer can perform either the watchdog timer function or the interval timer function. 8.2 16-Bit Timer/Event Counter Functions The 16-bit timer/event counter (TM0) has the following functions. * Interval timer * PWM output * Pulse width measurement * External event counter
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* Square-wave output PWM output and pulse width measurement functions at the same time.
(1) Interval timer TM0 generates interrupt requests at the preset time interval.
Table 8-2. 16-Bit Timer/Event Counter Interval Times
Minimum Interval Time 2 x TI0 input cycle 22 x 1/fX (400 ns) 23 x 1/fX (800 ns) 24 x 1/fX (1.6 s) Maximum Interval Time 216 x TI0 input cycle 217 x 1/fX (13.1 ms) 218 x 1/fX (26.2 ms) 219 x 1/fX (52.4 ms) Resolution TI0 input edge cycle 2 x 1/fX (200 ns) 22 x 1/fX (400 ns) 23 x 1/fX (800 ns)
Remarks
1. 2.
fX: Main system clock oscillation frequency Values in parentheses apply to operation with fX = 10.0 MHz
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(2) PWM output TM0 can generate 14-bit resolution PWM output. (3) Pulse width measurement TM0 can measure the pulse width of an externally input signal. (4) External event counter TM0 can measure the number of pulses of an externally input signal. (5) Square-wave output TM0 can output a square wave with any selected frequency.
Table 8-3. 16-Bit Timer/Event Counter Square-Wave Output Ranges
Minimum Pulse Width 2 x TI0 input cycle 22 x 1/fX (400 ns) 2 x 1/fX (800 ns)
3
Maximum Pulse Width 216 x TI0 input cycle 217 x 1/fX (13.1 ms) 218 x 1/fX (26.2 ms) 219 x 1/fX (52.4 ms)
Resolution TI0 input edge cycle 2 x 1/fX (200 ns) 22 x 1/fX (400 ns) 23 x 1/fX (800 ns)
24 x 1/fX (1.6 s)
Remarks
1. 2.
fX: Main system clock oscillation frequency Values in parentheses apply to operation with fX = 10.0 MHz
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8.3 16-Bit Timer/Event Counter Configuration The 16-bit timer/event counter consists of the following hardware.
Table 8-4. 16-Bit Timer/Event Counter Configuration
Item Timer register Register 16 bits x 1 (TM0) 16-bit compare register: 1 (CR00) 16-bit capture register: Timer output Control register 1 (TO0) Timer clock select register 0 (TCL0) 16-bit timer mode control register (TMC0) 16-bit timer output control register (TOC0) Port mode register 3 (PM3) External interrupt mode register (INTM0) Sampling clock select register (SCS)Note 1 (CR01) Configuration
Note
Refer to Figure 18-1 Basic Configuration of Interrupt Function.
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Selector
174
0 fX/2 fX/22 fX/23 TI0/P00/ INTP0
Note 1
Figure 8-1. 16-Bit Timer/Event Counter (Timer Mode) Block Diagram
Internal bus 15 16-bit compare register (CR00)
Match
Match
INTTM0
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0 16-bit timer register lower 8 bits (TM0L) Clear 3
78
15 16-bit timer register upper 8 bits (TM0H) Clear Selector 3 OVF
16-bit timer/event counter output control circuit
Note 2
TO0/P30
16-BIT TIMER/EVENT COUNTER
3
2
INTP0
0 TCL06 TCL05 TCL04
Timer clock select register 0
15 16-bit capture register (CR01) TMC03 TMC02 TMC01 OVF0 16-bit timer mode control register Internal bus LVS0 LVR0 TOC01 TOE0 16-bit timer output control register
Notes 1. Edge detector 2. The configuration of the 16-bit timer/event counter output control circuit is shown in Figure 8-3.
Figure 8-2. 16-Bit Timer/Event Counter (PWM Mode) Block Diagram
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Internal bus
16-bit compare register (CR00)
fX/2
PWM pulse generator
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Selector
fX/22 fX/23
Selector
TO0/ P30
16-bit timer register (TM0) 3
16-BIT TIMER/EVENT COUNTER
TCL06 TCL05 TCL04 Timer clock select register 0
16-bit capture register (CR01)
TOC01 TOE0 16-bit timer output control register Internal bus
P30 output latch
PM30 Port mode register 3
Remark
The circuitry enclosed by the dotted line is included in the output control circuit.
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LVS0 TOC01
S INV
Selector
Selector
176
LVR0 INTTM0 TI0/P00/ INTP0 Edge detector circuit 2 PWM pulse generator ES10, ES11
Figure 8-3. 16-Bit Timer/Event Counter Output Control Circuit Block Diagram
Level F/F (LV0) R Q
TO0/ P30
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P30 output latch 3
PM30
16-BIT TIMER/EVENT COUNTER
3 Active level control
TMC01 to TMC03
TOC01
TMC01 to TMC03
TOE0
Remark
The circuitry enclosed by the dotted line is the output control circuit.
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16-BIT TIMER/EVENT COUNTER
(1) 16-bit compare register (CR00) CR00 is a 16-bit register for which the value set in the CR00 is constantly compared with the 16-bit timer register (TM0) count value, and an interrupt request (INTTM0) is generated if they match. It can be used as the register which holds the interval time when TM0 is set to interval timer operation, and as the register which sets the pulse width when TM0 is set PWM output operation. CR00 is set by a 16-bit memory manipulation instruction. The value of 0001H to FFFFH can be set. After RESET input, the value of CR00 is undefined. Cautions 1. 2. 3. PWM data (14 bits) must be set in the upper 14 bits of CR00. The lower 2 bits must be set to 00. CR00 must be set in a value other than 0000H. Consequently, when it is used as an event counter, 1-pulse count operation is prohibited. When the value of CR00 posterior to alteration is less than the value of the 16-bit timer register (TM0), TM0 keeps on counting and resumes counting from 0 after an overflow. When the value of CR00 posterior to alteration is less than the value prior to alteration, the timer must be restarted after CR00 is altered. (2) 16-bit capture register (CR01) CR01 is a 16-bit register capturing the content of 16-bit timer register (TM0). Capture trigger is INTP0/P001/TI0 pin valid edge input. Setting of the INTP0 valid edge is done with the external interrupt mode register (INTM0). CR01 is read by a 16-bit memory manipulation instruction. After RESET input, the value of CR01 is undefined.
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Caution
When the TI0/P00 pin's valid edge is input while CR01 is read, CR01 retains its contents without doing capture operations. However, the interrupt request flag (PIF0) is set due to the valid edge detection.
(3) 16-bit timer register (TM0) TM0 is a 16-bit register counting count pulse. TM0 is read by a 16-bit memory manipulation instruction. After RESET input, the value of TM0 is 0000H. Caution The TM0 value is read out via CR01, resulting in changing the previous CR01 contents.
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8.4 16-Bit Timer/Event Counter Control Registers The following six types of registers are used to control the 16-bit timer/event counter. * Timer clock select register 0 (TCL0) * 16-bit timer mode control register (TMC0) * 16-bit timer output control register (TOC0) * Port mode register 3 (PM3) * External interrupt mode register (INTM0) * Sampling clock select register (SCS) (1) Timer clock select register 0 (TCL0) This register is used to set the count clock of the 16-bit timer register. TCL0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TCL0 to 00H. Remark TCL0 has the function of setting the PCL output clock in addition to that of setting the count clock of the 16-bit timer register.
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Figure 8-4. Timer Clock Select Register 0 Format
Symbol TCL0 <7> 6 5 4 3 2 1 0 Address FF40H When Reset 00H R/W R/W
CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00
TCL03 TCL02 TCL01 TCL00
PCL Output Clock Selection
0 0 1 1 1 1 1
0 1 0 0 0 0 1
0 1 0 0 1 1 0
0 1 0 1 0 1 0
fXT (32.768 kHz) fX/23 (1.25 MHz) fX/24 (625 kHz) fX/25 (313 kHz) fX/26 (156 kHz) fX/27 (78.1 kHz) fX/28 (39.1 kHz) Setting prohibited
Other than above
TCL06 TCL05 TCL04
16-bit Timer Register Count Clock Selection
0 0 0 1
0 1 1 0
0 0 1 0
TI0 (Valid edge specifiable) fX/2 (5.0 MHz) fX/22 (2.5 MHz) fX/23 (1.25 MHz) Setting prohibited
Other than above
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CLOE 0 1
PCL Output Control Output disabled Output enabled
Cautions 1.
Setting of the INTP0/P00/TI0 pin valid edge is performed by external interrupt mode register (INTM0), and selection of the sampling clock frequency is performed by the sampling clock selection register (SCS).
2. 3. 4.
When enabling PCL output, set TCL00 to TCL03, then set 1 in CLOE with a 1-bit memory manipulation instruction. To read the count value when TI0 has been specified as the TM0 count clock, the value should be read from TM0, not from the 16-bit capture register CR01. If data other than identical data is to be rewritten to TCL0, the timer operation must be stopped first.
Remarks
1. 2. 3. 4. 5. 6.
fX
: Main system clock oscillation frequency
fXT : Subsystem clock oscillation frequency TI0 : 16-bit timer/event counter input pin TM0: 16-bit timer register Value in parentheses apply to operation with fX = 10.0 MHz or fXT = 32.768 kHz. See CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT for PCL.
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(2) 16-bit timer mode control register (TMC0) This register sets the 16-bit timer operating mode, the 16-bit timer register clear mode and output timing, and detects an overflow. TMC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC0 value to 00H. Caution The 16-bit timer register (TM0) starts operation when TMC01 to TMC03 are set to the value other than 0, 0, 0 (operation stop mode). To stop the timer operation, set TMC01 through TCM03 to 0, 0, 0.
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Figure 8-5. 16-Bit Timer Mode Control Register Format
Symbol TMC0 7 0 6 0 5 0 4 0 3 2 1 <0> Address FF48H When Reset 00H R/W R/W
TMC03 TMC02 TMC01 OVF0
OVF0 0 1
16-Bit Timer Register Overflow Detection Overflow not detected Overflow detected
TMC03 TMC02 TMC01 Operating Mode & Clear Mode Selection 0 0 0 Operation stop (TM0 cleared to 0) 0 0 1 PWM mode (free running) 0 1 0 Free running mode
TO0 Output Timing Selection No change
Interrupt Request Generation Not generated
PWM pulse output
Generated on match between TM0 and CR00
Match between TM0 and CR00
0
1
1
Match between TM0 and CR00 or TI0 valid edge
1
0
0
Clear & start on TI0 valid edge
Match between TM0 and CR00 Match between TM0 and CR00 or TI0 valid edge
1
0
1
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1
1
0
Clear & start on match between TM0 and CR00
Match between TM0 and CR00 Match between TM0 and CR00 or TI0 valid edge
1
1
1
Cautions 1. 2. 3. 4.
Switch the clear mode and the TO0 output timing after stopping the timer operation (by setting TMC01 through TMC03 to 0, 0, 0). Set the valid edge of the INTP0/P00/TI0 pin with an external interrupt mode register (INTM0) and select the sampling clock frequency with a sampling clock select register (SCS). When using the PWM mode, set the PWM mode and then set data to CR00. If clear & start mode on match between TM0 and CR00 is selected, OVF0 flag is set to 1 when the set value of CR00 is FFFFH and the value of TM0 changes from FFFFH to 0000H.
Remarks
1. 2. 3. 4.
TO0 TI0 TM0
: : :
16-bit timer/event counter output pin 16-bit timer/event counter input pin 16-bit timer register 16-bit compare register
CR00 :
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(3) 16-bit timer output control register (TOC0) This register controls the operation of the 16-bit timer/event counter output control circuit. It sets R-S type flipflop (LV0) setting/resetting, the active level in PWM mode, output inversion enabling/disabling in modes other than PWM mode and data output mode. TOC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TOC0 value to 00H.
Figure 8-6. 16-Bit Timer Output Control Register Format
Symbol TOC0 7 0 6 0 5 0 4 0 <3> LVS0 <2> 1 <0> Address FF4EH When Reset 00H R/W R/W
LVR0 TOC01 TOE0
TOE0 0 1
16-Bit Timer/Event Counter Output Control Output disabled (Port mode) Output enabled
TOC01 In PWM Mode Active level selection 0 Active high
In Other Modes Timer output F/F control
Inversion operation disabled
1
Active low
Inversion operation enabled
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LVS0
LVR0
16-Bit Timer/Event Counter Timer Output F/F Status Setting
0 0 1 1
0 1 0 1
No change Timer output F/F reset (0) Timer output F/F set (1) Setting prohibited
Cautions 1. 2.
Timer operation must be stopped before setting TOC0. If LVS0 and LVR0 are read after data is set, they will be 0.
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(4) Port mode register 3 (PM3) This register sets port 3 input/output bit-wise. When using the P30/TO0 pin for timer output, set PM30 and output latch of P30 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 value to FFH.
Figure 8-7. Port Mode Register 3 Format
Symbol PM3 7 PM37 6 PM36 5 PM35 4 PM34 3 PM33 2 PM32 1 PM31 0 PM30 Address FF23H When Reset FFH R/W R/W
PM3n
P3n Pin Input/Output Mode Selection (n = 0 to 7)
0 1
Output mode (output buffer ON) Input mode (output buffer OFF)
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(5) External interrupt mode register (INTM0) This register is used to set INTP0 to INTP2 valid edges. INTM0 is set with an 8-bit memory manipulation instruction. RESET input sets INTM0 value to 00H. Remarks 1. INTP0 pin is a dual function pin also used for TI0/P00. 2. INTP3 is fixed at the falling edge.
Figure 8-8. External Interrupt Mode Register Format
Symbol INTM0
7 ES31
6 ES30
5 ES21
4 ES20
3 ES11
2 ES10
1 0
0 0
Address FFECH
When Reset 00H
R/W R/W
ES11 0 0 1 1
ES10 0 1 0 1
INTP0 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edge
ES21 0 0
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ES20 0 1 0 1
INTP1 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edge
1 1
ES31 0 0 1 1
ES30 0 1 0 1
INTP2 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edge
Caution
To specify the INTP0/P00/TI0 pin valid edge, bit 1 to bit 3 (TMC01 to TMC03) of the 16-bit timer mode control register (TMC0) must be set to 0, 0, 0, respectively after timer operaton is stopped.
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(6) Sampling clock select register (SCS) This register sets clocks which undergo clock sampling of valid edges to be input to INTP0. When remote controlled reception is carried out using INTP0, digital noise is removed with sampling clock. SCS is set with an 8-bit memory manipulation instruction. RESET input sets SCS value to 00H.
Figure 8-9. Sampling Clock Select Register Format
Symbol SCS 7 0 6 0 5 0 4 0 3 0 2 0 1 SCS1 0 SCS0 Address FF47H When Reset 00H R/W R/W
SCS1 0 0 1 1
SCS0 0 1 0 1
INTP0 Sampling Clock Selection fX/2N+1 Setting prohibited fX/26 (156 kHz) fX/27 (78.1 kHz)
Caution
fX/2N+1 is the clock supplied to the CPU, and fX/26 and fX/27 are clocks supplied to peripheral hardware. fX/2N+1 is stopped in HALT mode.
Remarks
1. 2.
N: Value set in bit 0 to bit 2 (PCC0 to PCC2) of the processor clock control register (PCC) (N = 0 to 4) fX: Main system clock oscillation frequency Values in parentheses apply to operation with fX = 10.0 MHz.
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3.
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8.5 16-Bit Timer/Event Counter Operations 8.5.1 Interval timer operations By setting bits 2 and 3 (TMC02 and TMC03) of the 16-bit timer mode control register (TMC0) to 1 and 1, they are operated as an interval timer. Interrupt requests are generated repeatedly using the count value set in 16-bit compare register (CR00) beforehand is used as the interval. When the count value of the 16-bit timer register (TM0) matches the value set to CR00, counting continues with the TM0 value cleared to 0 and the interrupt request signal (INTTM0) is generated. Count clock of the 16-bit timer/event counter can be selected with bits 4 to 6 (TCL04 to TCL06) of the timer clock select register 0 (TCL0). For the operation after changing compare register value during timer count operation, refer to 8.6 16-Bit Timer/ Event Counter Operating Precautions (3).
Figure 8-10. Interval Timer Configuration Diagram
16-bit compare register (CR00)
INTTM0 fX/2 fX/22 fX/23
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Selector
16-bit timer register (TM0)
OVF0
TI0/P00/INTP0 Clear circuit
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Figure 8-11. Interval Timer Operation Timings
t
Count clock
TM0 Count value
0000
0001
N
0000 0001 Clear N
N
0000 0001 Clear N
N
Count start CR00 N
N
INTTM0 Interrupt request acknowledge TO0 Interrupt request acknowledge
Interval time
Interval time
Interval time
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Remark
Interval time = (N + 1) x t : N = 0001H to FFFFH.
Table 8-5. 16-Bit Timer/Event Counter Interval Times
TCL06 0 0 0 1 TCL05 0 1 1 0 TCL04 0 0 1 0 Minimum Interval Time 2 x TI0 input cycle 22 x 1/fX (400 ns) 2 x 1/fX (800 ns)
3
Maximum Interval Time 2
16
Resolution TI0 input edge cycle 2 x 1/fX (200 ns) 22 x 1/fX (400 ns) 23 x 1/fX (800 ns)
x TI0 input cycle x 1/fX (26.2 ms)
217 x 1/fX (13.1 ms) 2
18
24 x 1/fX (1.6 s) Setting prohibited
219 x 1/fX (52.4 ms)
Other than above
Remarks
1. 2. 3.
fX: Main system clock oscillation frequency TCL04 to TCL06: Bits 4 to 6 of the timer clock select register 0 (TCL0) Values in parentheses apply to operation with fX = 10.0 MHz
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8.5.2 PWM output operations By setting bits 1 to 3 (TMC01 to 03) of the 16-bit timer mode control register (TMC0) to 1, 0, and 0, they are operated as PWM output. Pulses with the duty rate determined by the value set in 16-bit compare register (CR00) beforehand are output from the TO0/P30 pin. Set the active level width of the PWM pulse to the high-order 14 bits of CR00. Select the active level with bit 1 (TOC01) of the 16-bit timer output control register (TOC0). This PWM pulse has a 14-bit resolution. The pulse can be converted to an analog voltage by integrating it with an external low-pass filter (LPF). The PWM pulse has a combination of the basic cycle determined by 28/f and the sub-cycle determined by 214/f so that the time constant of the external LPF can be shortened. Count clock f can be selected with bits 4 to 6 (TCL04 to TCL06) of the timer clock select register 0 (TCL0). PWM output enable/disable can be selected with bit 0 (TOE0) of TOC0. Cautions 1. 2. 3. PWM operation mode should be selected before setting CR00. Be sure to write 0 to bits 0 and 1 of CR00. Do not select PWM operation mode for external clock input from the INTP0/P00/TI0 pin.
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By integrating 14-bit resolution PWM pulses with an external low-pass filter, they can be converted to an analog voltage and used for electronic tuning and D/A converter applications, etc. The analog output voltage (VAN) used for D/A conversion with the configuration shown in Figure 8-12 is as follows. VAN = VREF x 16-bit compare register (CR00) value 216 VREF: External switching circuit reference voltage
Figure 8-12. Example of D/A Converter Configuration with PWM Output
PD78014,78014Y
VREF
PWM signal TO0/P30 Switching circuit Low-pass filter
Analog output (VAN)
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Figure 8-13 shows an example in which PWM output is converted to an analog voltage and used in a voltage synthesizer type TV tuner.
Figure 8-13. TV Tuner Application Circuit Example
+110 V
PD78014,78014Y
22 k 47 k 100 pF TO0/P30 8.2 k 8.2 k VSS GND 2SC 2352 0.22 F 0.22 F 0.22 F Electronic Tuner 47 k 47 k
PC574J
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8.5.3 Pulse width measurement operations The pulse width of the signal to be input to theINTP0/P00/TI0 pin can be neasured with the 16-bit timer register (TM0). There are two measurement methods: measuring with TM0 used in free-running mode, and measuring by restarting the timer in synchronization with the valid edge of the signal input to the INTP0/P00/TI0 pin. (1) Pulse width measurement with free-running When the 16-bit timer register (TM0) is operated, the edge specified by external interrupt mode register (INTM0) is input, the value of TM0 is taken into 16-bit capture register (CR01) and an external interrupt request signal (INTP0) is set. Any of three edge specifications can be selected - rising, falling, or both edges - by means of bits 2 and 3 (ES10 and ES11) of the external interrupt mode register (INTM0). For valid edge detection, sampling is performed at the interval selected by means of the sampling clock select register (SCS), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width.
Figure 8-14. Configuration Diagram for Pulse Width Measurement by Free-Running Counter
fX/22 fX/23
Selector
fX/2
16-Bit Timer Register (TM0)
OVF0
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TI0/P00/INTP0
16-Bit Capture Register (CR01)
INTP0
Internal Bus
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Figure 8-15. Timing of Pulse Width Measurement Operation by Free-Running Counter (with Both Edges Specified)
t
Count Clock
TM0 Count Value
0000 0001
D0
D1
FFFF 0000
D2
D3
TI0 Pin Input
CR01 Captured Value
D0
D1
D2
D3
INTP0
OVF0
(D1 - D0) x t
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(10000H - D1 + D2) x t
(D3 - D2) x t
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(2) Pulse width measurement by means of restart When input of a valid edge to the INTP0/P00/TI0 pin is detected, the count value of the 16-bit timer register (TM0) is taken into the 16-bit capture register (CR01), and then the pulse width of the signal input to the INTP0/P00/ TI0 pin is measured by clearing TM0 and restarting the count. The edge specification can be selected from three types, rising, falling, and both edges by bit 2 and bit 3 (ES10 and ES11) of the external interrupt mode register (INTM0). In a valid edge detection, the sampling is performed by a cycle selected by the sampling clock select register (SCS), and a capture operation is not performed before detecting valid levels twice allowing short pulse width noise to be eliminated.
Figure 8-16.
Timing of Pulse Width Measurement Operation by Means of Restart (with Both Edges Specified)
t
Count Clock
TM0 Count Value
0000 0001
D0
0000 0001
D1
0000 0001
TI0 Pin Input
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CR01 Captured Value
D0
D1
INTP0
(D0 + 1) x t
(D1 + 1) x t
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8.5.4 External event counter operation The external event counter counts the number of external clock pulses to be input to the INTP0/P00/TI0 pin with the 16-bit timer register (TM0). TM0 is incremented each time the valid edge specified with the external interrupt mode register (INTM0) is input. When the TM0 counted value matches the 16-bit compare register (CR00) value, TM0 is cleared to 0 and the interrupt request signal (INTTM0) is generated. The 16-bit compare register (CR00) must be set to a value other than 0000H (1-pulse count operation is prohibited). The rising edge, the falling edge or both edges can be selected with bits 2 and 3 (ES10 and ES11) of INTM0. Because operation is carried out only after the valid edge is detected twice by sampling at the cycle selected with the sampling clock select register (SCS), noise with short pulse widths can be removed.
Figure 8-17. External Event Counter Configuration Diagram
16-Bit Compare Register (CR00)
Clear
INTTM0
TI0 Valid Edge
16-Bit Timer Register (TM0)
OVF0 INTP0
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16-Bit Capture Register (CR01)
Internal Bus
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Figure 8-18. External Event Counter Operation Timings (with Rising Edge Specified)
TI0 Pin Input
TM0 Count Value
0000 0001 0002 0003
0004
0005
N-1
N
0000 0001 0002 0003
CR00
N
INTTM0
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8.5.5 Square-wave output operation The 16-bit timer/event counter operates as a square wave with any selected frequency which is output at intervals of the count value preset to the 16-bit compare register (CR00). The TO0/P30 pin output status is inverted at intervals of the count value preset to CR00 by setting bit 0 (TOE0) and bit 1 (TOC01) of the 16-bit timer output control register to 1. This enables a square wave with any selected frequency to be output.
Table 8-6. 16-Bit Timer/Event Counter Square-Wave Output Ranges
TCL06 0 0 0 1 TCL05 0 1 1 0 TCL04 0 0 1 0 Minimum Pulse Width 2 x TI0 input cycle 22 x 1/fX (400 ns) 23 x 1/fX (800 ns) 2 x 1/fX (1.6 s)
4
Maximum Pulse Width 216 x TI0 input cycle 217 x 1/fX (13.1 ms) 218 x 1/fX (26.2 ms) 2
19
Resolution TI0 input edge cycle 2 x 1/fX (200 ns) 22 x 1/fX (400 ns) 23 x 1/fX (800 ns)
x 1/fX (52.4 ms)
Remarks
1. 2. 3.
fX: Main system clock oscillation frequency TCL04 to TCL06: Bit 4 to bit 6 of timer clock select register 0 (TCL0) Values in parentheses apply to operation with fX = 10.0 MHz
Figure 8-19. Square-Wave Output Operation Timings
Count Clock
TM0 Count Value
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0000
0001 0002
N-1
N
0000
0001 0002
N-1
N
0000
Count Start CR00 N N
TO0Note
Note
Initial value of TO0 output can be set at bits 2 and 3 (LVR0 and LVS0) of the 16-bit timer output control register (TOC0).
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8.6 16-Bit Timer/Event Counter Operating Precautions (1) Timer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start. This is because the 16-bit timer register (TM0) is started asynchronously with the count pulse.
Figure 8-20. 16-Bit Timer Register Start Timings
Count Pulse
TM0 Count Value
0000H
0001H
0002H
0003H
0004H
Timer Start
(2) 16-bit compare register set Set a value other than 0000H to the 16-bit compare register (CR00). Thus, when using the 16-bit compare register as event counter, one-pulse count operation cannot be carried out. (3) Operation after compare register change during timer count operation If the value after the 16-bit compare register (CR00) is changed is smaller than that of the 16-bit timer register (TM0), TM0 continues counting and then restarts counting from 0. Therefore, if the value after CR00 changes (M) is smaller than the value before change (N), it is necessary to restart the timer after changing CR00.
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Figure 8-21. Timings after Change of Compare Register during Timer Count Operation
Count Pulse
CR00
N
M
TM0 Count Value
X-1
X
FFFFH
0000H
0001H
0002H
Remark
N>X>M
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(4) Capture register data retention timings If the valid edge of the TI0/P00 pin is input during 16-bit capture register (CR01) read, CR01 holds data without carrying out capture operation. However, the interrupt request flag (PIF0) is set upon detection of the valid edge.
Figure 8-22. Capture Register Data Retention Timings
Count Pulse
TM0 Count Value Edge Input Interrupt Request Flag
N
N+1
N+2
M
M+1
M+2
Capture Read Signal
CR01 Captured Value
X
N+1
Capture Operation Ignored
(5) Valid edge set Set the valid edge of the TI0/INTP0/P00 pin after setting bits 1 to 3 (TMC01 to TMC03) of the 16-bit timer mode
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control register (TMC0) to 0, 0 and 0, respectively, and then stopping timer operation. Valid edge setting is carried out with bits 2 and 3 (ES10 and ES11) of the external interrupt mode register (INTM0).
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(6) OVF0 flag operation OVF0 flag is set to 1: When clear & start mode on match between TM0 and CR00 is selected CR00 is set to FFFFH TM0 is counted up from FFFFH to 0000H
Figure 8-23. OVF0 Flag Operation Timing
Count Pulse
CR00
FFFFH
TM0
FFFEH
FFFFH
0000H
0001H
OVF0
INTTM00
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9.1 8-Bit Timer/Event Counter Functions
For the 8-bit timer/event counter incorporated in the PD78014 and 78014Y Subseries, the following two modes are available. * 8-bit timer/event counter mode * 16-bit timer/event counter mode : two-channel 8-bit timer/event counters to be used separately : two-channel 8-bit timer/event counters to be used together as 16-bit timer/ event counter 9.1.1 8-bit timer/event counter mode The 8-bit timer/event counters 1 and 2 (TM1 and TM2) have the following functions. * Interval timer * External event counter * Square-wave output
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(1) 8-bit interval timer Interrupt requests are generated at the preset time intervals.
Table 9-1. 8-Bit Timer/Event Counter Interval Times
Minimum Interval Time 22 x 1/fX (400 ns) 23 x 1/fX (800 ns) 24 x 1/fX (1.6 s) 2 x 1/fX (3.2 s)
5
Maximum Interval Time 210 x 1/fX (102.4 s) 211 x 1/fX (204.8 s) 212 x 1/fX (409.6 s) 2
13
Resolution 22 x 1/fX (400 ns) 23 x 1/fX (800 ns) 24 x 1/fX (1.6 s) 25 x 1/fX (3.2 s) 26 x 1/fX (6.4 s) 27 x 1/fX (12.8 s) 28 x 1/fX (25.6 s) 29 x 1/fX (51.2 s) 210 x 1/fX (102.4 s) 212 x 1/fX (409.6 s)
x 1/fX (819.2 s) x 1/fX (3.28 ms) x 1/fX (13.1 ms) x 1/fX (104.9 ms)
26 x 1/fX (6.4 s) 2 x 1/fX (12.8 s)
7
214 x 1/fX (1.64 ms) 2
15
28 x 1/fX (25.6 s) 2 x 1/fX (51.2 s)
9
216 x 1/fX (6.55 ms) 2
17
210 x 1/fX (102.4 s) 2
12
218 x 1/fX (26.2 ms) 2
20
x 1/fX (409.6 s)
Remarks
1. 2.
fX: Main system clock oscillation frequency Values in parentheses apply to operation with fX = 10.0 MHz.
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(2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output.
Table 9-2. 8-Bit Timer/Event Counter Square-Wave Output Ranges
Minimum Pulse Width 2 x 1/fX (400 ns)
2
Maximum Pulse Width 2
10
Resolution 2 x 1/fX (400 ns)
2
x 1/fX (102.4 s)
23 x 1/fX (800 ns) 24 x 1/fX (1.6 s) 2 x 1/fX (3.2 s)
5
211 x 1/fX (204.8 s) 212 x 1/fX (409.6 s) 2
13
23 x 1/fX (800 ns) 24 x 1/fX (1.6 s) 25 x 1/fX (3.2 s) 26 x 1/fX (6.4 s) 27 x 1/fX (12.8 s) 28 x 1/fX (25.6 s) 29 x 1/fX (51.2 s) 210 x 1/fX (102.4 s) 212 x 1/fX (409.6 s)
x 1/fX (819.2 s) x 1/fX (3.28 ms) x 1/fX (13.1 ms) x 1/fX (104.9 ms)
26 x 1/fX (6.4 s) 2 x 1/fX (12.8 s)
7
214 x 1/fX (1.64 ms) 2
15
28 x 1/fX (25.6 s) 2 x 1/fX (51.2 s)
9
216 x 1/fX (6.55 ms) 2
17
210 x 1/fX (102.4 s) 2
12
218 x 1/fX (26.2 ms) 2
20
x 1/fX (409.6 s)
Remarks
1. 2.
fX: Main system clock oscillation frequency Values in parentheses apply to operation with fX = 10.0 MHz.
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9.1.2 16-bit timer/event counter mode (1) 16-bit interval timer Interrupt requests can be generated at the preset time intervals.
Table 9-3. Interval Times when 8-Bit Timer/Event Counters are Used as 16-Bit Timer/Event Counter
Minimum Interval Time 22 x 1/fX (400 ns) 23 x 1/fX (800 ns) 24 x 1/fX (1.6 s) 2 x 1/fX (3.2 s)
5
Maximum Interval Time 218 x 1/fX (26.2 ms) 219 x 1/fX (52.4 ms) 220 x 1/fX (104.9 ms) 2
21
Resolution 22 x 1/fX (400 ns) 23 x 1/fX (800 ns) 24 x 1/fX (1.6 s) 25 x 1/fX (3.2 s) 26 x 1/fX (6.4 s) 27 x 1/fX (12.8 s) 28 x 1/fX (25.6 s) 29 x 1/fX (51.2 s) 210 x 1/fX (102.4 s) 212 x 1/fX (409.6 s)
x 1/fX (209.7 ms) x 1/fX (838.9 ms) x 1/fX (3.7 s) x 1/fX (26.8 s)
26 x 1/fX (6.4 s) 2 x 1/fX (12.8 s)
7
222 x 1/fX (419.4 ms) 2
23
28 x 1/fX (25.6 s) 2 x 1/fX (51.2 s)
9
224 x 1/fX (1.7 s) 2
25
210 x 1/fX (102.4 s) 2
12
226 x 1/fX (6.7 s) 2
28
x 1/fX (409.6 s)
Remarks
1. 2.
fX: Main system clock oscillation frequency Values in parentheses apply to operation with fX = 10.0 MHz.
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(2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output.
Table 9-4. Square-Wave Output Ranges when 8-Bit Timer/Event Counters are Used as 16-Bit Timer/Event Counter
Minimum Pulse Width 2 x 1/fX (400 ns)
2 3 4
Maximum Pulse Width 2 2 2
18 19 20
Resolution 2 x 1/fX (400 ns)
2
x 1/fX (26.2 ms) x 1/fX (52.4 ms) x 1/fX (104.9 ms) x 1/fX (419.4 ms) x 1/fX (1.7 s) x 1/fX (6.7 s)
2 x 1/fX (800 ns) 2 x 1/fX (1.6 s) 25 x 1/fX (3.2 s) 2 x 1/fX (6.4 s)
6
23 x 1/fX (800 ns) 24 x 1/fX (1.6 s) 25 x 1/fX (3.2 s) 26 x 1/fX (6.4 s) 27 x 1/fX (12.8 s) 28 x 1/fX (25.6 s) 29 x 1/fX (51.2 s) 210 x 1/fX (102.4 s) 212 x 1/fX (409.6 s)
221 x 1/fX (209.7 ms) 2
22
27 x 1/fX (12.8 s) 2 x 1/fX (25.6 s)
8
223 x 1/fX (838.9 ms) 2
24
29 x 1/fX (51.2 s) 2
10
225 x 1/fX (3.4 s) 2
26
x 1/fX (102.4 s)
212 x 1/fX (409.6 s)
228 x 1/fX (26.8 s)
Remarks
1. 2.
fX: Main system clock oscillation frequency Values in parentheses apply to operation with fX = 10.0 MHz.
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9.2 8-Bit Timer/Event Counter Configuration
The 8-bit timer/event counter consists of the following hardware.
Table 9-5. 8-Bit Timer/Event Counter Configuration
Item Timer register Register Timer output Control registers Configuration 8-bits x 2 (TM1, TM2) 8-bit compare register: 2 (CR10, CR20) 2 (TO1, TO2) Timer clock select register 1 (TCL1) 8-bit timer mode control register (TMC1) 8-bit timer output control register (TOC1) Port mode register 3 (PM3)Note
Note
Refer to Figure 6-10 P30 to P37 Block Diagrams.
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Figure 9-1. 8-Bit Timer/Event Counter Block Diagram
Internal Bus INTTM1 8-Bit Compare Register (CR10) 8-Bit Compare Register (CR20)
Note
Match fX/22 to fX/210 fX/212 TI1/P33 4 Selector
Selector
Selector
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Match
Selector
8-Bit Timer/Event Counter Output Control Circuit 2
TO2/P32 CHAPTER 9
Selector
8-Bit Timer Register 1 (TM1) Clear
4 8-Bit Timer Register 1 (TM2) Clear INTTM2
8-BIT TIMER/EVENT COUNTER
fX/22 to fX/210 fX/212 TI2/P34
Note
4
8-Bit Timer/Event Counter Output Control Circuit 1 4
TO1/P31
TCL TCL TCL TCL TCL TCL TCL TCL 17 16 15 14 13 12 11 10 Timer Clock Select Register 1
TMC12 TCE2 TCE1 8-Bit Timer Mode Control Register Internal Bus
TOC TOC TOE1 TOE2 LVS1 LVR1 LVS2 LVR2 11 15
8-Bit Timer Output Control Register
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Note
Refer to Figures 9-2 and 9-3 for details of 8-bit timer/event counter output control circuits 1 and 2, respectively.
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Figure 9-2. 8-Bit Timer/Event Counter Output Control Circuit 1 Block Diagram
Level F/F (LV1) LVR1 LVS1 TOC11 R Q S INV P31 Output Latch PM31Note TO1/P31
INTTM1
TOE1
Note Remark
Bit 1 of the port mode register 3 (PM3) The section in the broken line is an output control circuit.
Figure 9-3. 8-Bit Timer/Event Counter Output Control Circuit 2 Block Diagram
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Level F/F (LV2) LVR2 LVS2 TOC15 R Q S INV
fSCK
TO2/P32 P32 Output Latch PM32Note
INTTM2
TOE2
Note
Bit 2 of the port mode register 3 (PM3) 1. 2. The section in the broken line is an output control circuit. fSCK: Serial clock frequency
Remarks
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(1) 8-bit compare registers (CR10, CR20) These are 8-bit registers that compare the value set to CR10 with the 8-bit timer register 1 (TM1) count value, and the value set to CR20 with the 8-bit timer register 2 (TM2) count value, and, if they match, generate an interrupt request (INTTM1 and INTTM2, respectively). When TM1 and TM2 are set to interval timer operation, they can be used as registers to hold interval time. CR10 and CR20 are set with an 8-bit memory manipulation instruction. They cannot be set with a 16-bit memory manipulation instruction. When the compare register is used as an 8-bit timer/event counter, the 00H to FFH values can be set. When the compare registers are used as 16-bit timer/event counter, the 0000H to FFFFH values can be set. RESET input makes CR10 and CR20 undefined. Cautions 1. 2. When using the compare registers as 16-bit timer/event counter, be sure to set data after stopping timer operation. When the values of CR10 and CR20 posterior to alteration are less than the values of the 8-bit timer registers (TM1 and TM2), TM1 and TM2 keep on counting and resume counting from 0 after an overflow. When the values of CR10 and CR20 posterior to alteration are less than the values prior to alteration, the timer must be restarted after CR10 and CR20 are altered. (2) 8-bit timer registers 1, 2 (TM1, TM2) These are 8-bit registers to count count pulses. When TM1 and TM2 are used in the 8-bit timer x 2-channel mode, they are read with an 8-bit memory manipulation instruction. When TM1 and TM2 are used as 16-bit timer x 1-channel mode, 16-bit timer register (TMS) is read with a 16-bit memory manipulation instruction.
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RESET input sets TM1 and TM2 to 00H.
9.3 8-Bit Timer/Event Counter Control Registers
The following four types of registers are used to control the 8-bit timer/event counter. * Timer clock select register 1 (TCL1) * 8-bit timer mode control register (TMC1) * 8-bit timer output control register (TOC1) * Port mode register 3 (PM3) (1) Timer clock select register 1 (TCL1) This register sets count clocks of 8-bit timer registers 1 and 2. TCL1 is set with an 8-bit memory manipulation instruction. RESET input sets TCL1 to 00H.
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Figure 9-4. Timer Clock Select Register 1 Format
Symbol TCL1 7 6 5 4 3 2 1 0 Address FF41H When Reset 00H R/W R/W
TCL17 TCL16 TCL15 TCL14 TCL13 TCL12 TCL11 TCL10
TCL13 TCL12 TCL11 TCL10
8-bit Timer Register 1 Clock Selection
0 0 0 0 1 1 1 1 1 1 1 1
0 0 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1
TI1 falling edge TI1 rising edge fX/22 (2.5 MHz) fX/23 (1.25 MHz) fX/24 (625 kHz) fX/25 (313 kHz) fX/26 (156 kHz) fX/27 (78.1 kHz) fX/28 (39.1 kHz) fX/29 (19.5 kHz) fX/210 (9.8 kHz) fX/212 (2.4 kHz) Setting prohibited
Other than above
TCL17 TCL16 TCL15 TCL14
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8-bit Timer Register 2 Clock Selection
0 0 0 0 1 1 1 1 1 1 1 1
0 0 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1
TI2 falling edge TI2 rising edge fX/22 (2.5 MHz) fX/23 (1.25 MHz) fX/24 (625 kHz) fX/25 (313 kHz) fX/26 (156 kHz) fX/27 (78.1 kHz) fX/28 (39.1 kHz) fX/29 (19.5 kHz) fX/210 (9.8 kHz) fX/212 (2.4 kHz) Setting prohibited
Other than above
Caution
If data other than identical data is to be rewritten to TCL1, the timer operation must be stopped first.
Remarks
1. 2. 3. 4.
fX
: Main system clock oscillation frequency
TI1 : 8-bit timer register 1 input pin TI2 : 8-bit timer register 2 input pin Values in parentheses apply to operation with fX = 10.0 MHz.
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(2) 8-bit timer mode control register (TMC1) This register enables/stops operation of 8-bit timer registers 1 and 2 and sets the operating mode of 8-bit timer registers 1 and 2. TMC1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC1 to 00H.
Figure 9-5. 8-Bit Timer Mode Control Register Format
Symbol TMC1 7 0 6 0 5 0 4 0 3 0 2 <1> <0> TCE1 Address FF49H When Reset 00H R/W R/W
TMC12 TCE2
TCE1 0 1
8-Bit Timer Register 1 Operation Control Operation stop (TM1 clear to 0) Operation enable
TCE2 0 1
8-Bit Timer Register 2 Operation Control Operation stop (TM2 clear to 0) Operation enable
TMC12 Operating Mode Selection 0 8-Bit timer register x 2-channel mode (TM1, TM2) 1
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16-Bit timer register x 1-channel mode (TMS)
Cautions 1. 2.
Switch the operating mode after stopping timer operation. When used as 16-bit timer register (TMS), TCE1 should be used for operation enable/stop.
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(3) 8-bit timer output control register (TOC1) This register controls operation of 8-bit timer/event counter output control circuits 1 and 2. It sets/resets the R-S flip-flops (LV1 and LV2) and enables/disables inversion and 8-bit timer output of 8-bit timer registers 1 and 2. TOC1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TOC1 to 00H.
Figure 9-6. 8-Bit Timer Output Control Register Format
Symbol TOC1 <7> LVS2 <6> 5 <4> <3> LVS1 <2> 1 <0> Address FF4FH When Reset 00H R/W R/W
LVR2 TOC15 TOE2
LVR1 TOC11 TOE1
TOE1 0 1
8-Bit Timer/Event Counter 1 Output Control Output disable (port mode) Output enable
TOC11 8-Bit Timer/Event Counter 1 Timer Output F/F Control 0 1 Inverted operation disable Inverted operation enable
LVS1
LVR1
8-Bit Timer/Event Counter 1 Timer Output F/F Status Set
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0 0 1 1
0 1 0 1
Unchanged Timer output F/F reset (0) Timer output F/F reset (1) Setting prohibited
TOE2 0 1
8-Bit Timer/Event Counter 2 Output Control Output disable (port mode) Output enable
TOC15 8-Bit Timer/Event Counter 2 Timer Output F/F Status Control 0 1 Inverted operation disable Inverted operation enable
LVS2
LVR2
8-Bit Timer/Event Counter 2 Timer Output F/F Status Set
0 0 1 1
0 1 0 1
Unchanged Timer output F/F reset (0) Timer output F/F reset (1) Setting prohibited
Cautions 1. 2.
Be sure to set TOC1 after stopping timer operation. After data setting, 0 can be read from LVS1, LVS2, LVR1, and LVR2.
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(4) Port mode register 3 (PM3) This register sets port 3 input/output bit-wise. When using the P31/TO1 and P32/TO2 pins for timer output, set output latches PM31, PM32, and P31, P32 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH.
Figure 9-7. Port Mode Register 3 Format
Symbol PM3 7 PM37 6 PM36 5 PM35 4 PM34 3 PM33 2 PM32 1 PM31 0 PM30 Address FF23H When Reset FFH R/W R/W
PM3n
P3n Pin Input/Output Mode Selection (n = 0 to 7)
0 1
Output mode (output buffer ON) Input mode (output buffer OFF)
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9.4 8-Bit Timer/Event Counter Operations
9.4.1 8-bit timer/event counter mode (1) Interval timer operations The 8-bit timer/event counter operates as an interval timer which generates interrupt requests repeatedly at intervals of the count value preset to 8-bit compare registers (CR10 and CR20). When the count values of the 8-bit timer registers 1 and 2 (TM1 and TM2) match the values set to CR10 and CR20, counting continues with the TM1 and TM2 values cleared to 0 and the interrupt request signals (INTTM1 and INTTM2) are generated. Count clock of TM1 can be selected with bits 0 to 3 (TCL10 toTCL13) of the timer clock select register 1 (TCL1). Count clock of TM2 can be selected with bits 4 to 7 (TCL14 toTCL17) of the timer clock select register 1 (TCL1). For the operation after changing compare register value during timer count operation, refer to 9.5 Cautions on 8-Bit Timer/Event Counter (3).
Figure 9-8. Interval Timer Operation Timings
t
Count Clock
TM1 Count Value
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00
01
N
00 Clear
01
N
00 Clear
01
N
Count Start
CR10
N
N
N
N
INTTM1 Interrupt Request Acknowledge TO1 Interrupt Request Acknowledge
Interval Time
Interval Time
Interval Time
Remark
Interval time = (N + 1) x t : N = 00H to FFH
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Table 9-6. 8-Bit Timer/Event Counter 1 Interval Times
TCL13 0 0 0 0 1 1 1 1 1 1 1 1 TCL12 0 0 1 1 0 0 0 0 1 1 1 1 TCL11 0 0 1 1 0 0 1 1 0 0 1 1 TCL10 0 1 0 1 0 1 0 1 0 1 0 1 Minimum Interval Time TI1 input cycle TI1 input cycle 22 x 1/fX (400 ns) 23 x 1/fX (800 ns) 24 x 1/fX (1.6 s) 2 x 1/fX (3.2 s)
5
Maximum Interval Time 28 x TI1 input cycle 28 x TI1 input cycle 210 x 1/fX (102.4 s) 211 x 1/fX (204.8 s) 212 x 1/fX (409.6 s) 2
13
Resolution TI1 input edge cycle TI1 input edge cycle 22 x 1/fX (400 ns) 23 x 1/fX (800 ns) 24 x 1/fX (1.6 s) 25 x 1/fX (3.2 s) 26 x 1/fX (6.4 s) 27 x 1/fX (12.8 s) 28 x 1/fX (25.6 s) 29 x 1/fX (51.2 s) 210 x 1/fX (102.4 s) 212 x 1/fX (409.6 s)
x 1/fX (819.2 s) x 1/fX (3.28 ms) x 1/fX (13.1 ms) x 1/fX (104.9 ms)
26 x 1/fX (6.4 s) 2 x 1/fX (12.8 s)
7
214 x 1/fX (1.64 ms) 2
15
28 x 1/fX (25.6 s) 2 x 1/fX (51.2 s)
9
216 x 1/fX (6.55 ms) 2
17
210 x 1/fX (102.4 s) 2
12
218 x 1/fX (26.2 ms) 2
20
x 1/fX (409.6 s)
Other than above
Setting prohibited
Remarks
1. 2. 3.
fX: Main system clock oscillation frequency TCL10 to TCL13: Bits 0 to 3 of the timer clock select register 1 (TCL1) Values in parentheses apply to operation with fX = 10.0 MHz.
Table 9-7. 8-Bit Timer/Event Counter 2 Interval Times
TCL17
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TCL16 0 0 1 1 0 0 0 0 1 1 1 1
TCL15 0 0 1 1 0 0 1 1 0 0 1 1
TCL14 0 1 0 1 0 1 0 1 0 1 0 1
Minimum Interval Time TI2 input cycle TI2 input cycle 2 x 1/fX (400 ns)
2
Maximum Interval Time 2 x TI2 input cycle
8
Resolution TI2 input edge cycle TI2 input edge cycle 22 x 1/fX (400 ns) 23 x 1/fX (800 ns) 24 x 1/fX (1.6 s) 25 x 1/fX (3.2 s) 26 x 1/fX (6.4 s) 27 x 1/fX (12.8 s) 28 x 1/fX (25.6 s) 29 x 1/fX (51.2 s) 210 x 1/fX (102.4 s) 212 x 1/fX (409.6 s)
0 0 0 0 1 1 1 1 1 1 1 1
28 x TI2 input cycle 2
10
x 1/fX (102.4 s) x 1/fX (409.6 s) x 1/fX (1.64 ms) x 1/fX (6.55 ms) x 1/fX (26.2 ms)
23 x 1/fX (800 ns) 2 x 1/fX (1.6 s)
4
211 x 1/fX (204.8 s) 2
12
25 x 1/fX (3.2 s) 2 x 1/fX (6.4 s)
6
213 x 1/fX (819.2 s) 2
14
27 x 1/fX (12.8 s) 2 x 1/fX (25.6 s)
8
215 x 1/fX (3.28 ms) 2
16
29 x 1/fX (51.2 s) 2
10
217 x 1/fX (13.1 ms) 2
18
x 1/fX (102.4 s)
212 x 1/fX (409.6 s) Setting prohibited
220 x 1/fX (104.9 ms)
Other than above
Remarks
1. 2. 3.
fX: Main system clock oscillation frequency TCL14 to TCL17: Bits 4 to 7 of the timer clock select register 1 (TCL1) Values in parentheses apply to operation with fX = 10.0 MHz.
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(2) External event counter operation The external event counter counts the number of external clock pulses to be input to the TI1/P33 and TI2/P34 pins with 8-bit timer registers 1 and 2 (TM1 and TM2). TM1 and TM2 are incremented each time the valid edge specified with the timer clock select register 1 (TCL1) is input. Either the rising or falling edge can be selected. When the TM1 and TM2 counted values match the values of 8-bit compare registers (CR10 and CR20), TM1 and TM2 are cleared to 0 and the interrupt request signals (INTTM1 and INTTM2) are generated.
Figure 9-9. External Event Counter Operation Timings (with Rising Edge Specified)
TI1 Pin Input
TM1 Count Value
00
01
02
03
04
05
N-1
N
00
01
02
03
CR10
N
INTTM1
Remark
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N = 00H to FFH
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(3) Square-wave output operation The 8-bit timer/event counter operates as a square wave with any selected frequency which is output at intervals of the value preset to 8-bit compare registers (CR10 and CR20). The TO1/P31 or TO2/P32 pin output status is inverted at intervals of the count value preset to CR10 or CR20 by setting bit 0 (TOE1) or bit 4 (TOE2) of the 8-bit timer output control register (TOC1) to 1. This enables a square wave with any selected frequency to be output.
Table 9-8. 8-Bit Timer/Event Counter Square-Wave Output Ranges
TCL13 0 0 1 1 1 1 1 1 1 1 TCL12 1 1 0 0 0 0 1 1 1 1 TCL11 1 1 0 0 1 1 0 0 1 1 TCL10 0 1 0 1 0 1 0 1 0 1 Minimum Pulse Width 22 x 1/fX (400 ns) 23 x 1/fX (800 ns) 24 x 1/fX (1.6 s) 2 x 1/fX (3.2 s)
5
Maximum Pulse Width 210 x 1/fX (102.4 s) 211 x 1/fX (204.8 s) 212 x 1/fX (409.6 s) 2
13
Resolution 22 x 1/fX (400 ns) 23 x 1/fX (800 ns) 24 x 1/fX (1.6 s) 25 x 1/fX (3.2 s) 26 x 1/fX (6.4 s) 27 x 1/fX (12.8 s) 28 x 1/fX (25.6 s) 29 x 1/fX (51.2 s) 210 x 1/fX (102.4 s) 212 x 1/fX (409.6 s)
x 1/fX (819.2 s) x 1/fX (3.28 ms) x 1/fX (13.1 ms) x 1/fX (104.9 ms)
26 x 1/fX (6.4 s) 2 x 1/fX (12.8 s)
7
214 x 1/fX (1.64 ms) 2
15
28 x 1/fX (25.6 s) 2 x 1/fX (51.2 s)
9
216 x 1/fX (6.55 ms) 2
17
210 x 1/fX (102.4 s) 2
12
218 x 1/fX (26.2 ms) 2
20
x 1/fX (409.6 s)
Remarks
1. 2. 3.
fX: Main system clock oscillation frequency TCL10 to TCL13: Bit 0 to bit 3 of timer clock select register 1 (TCL1) Values in parentheses apply to operation with fX = 10.0 MHz.
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Figure 9-10. Square-Wave Output Operation Timings
Count Clock
TM1 Count Value
00
01
02
N-1
N
00
01
02
N-1
N
00
Count Start CR10 N N
TO1Note
Note
Initial value of TO1 output can be set at bits 2 and 3 (LVS1 and LVR1) of the 8-bit timer output control register (TOC1).
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9.4.2 16-bit timer/event counter mode When bit 2 (TMC12) of the 8-bit timer mode control register (TMC1) is set to 1, the 16-bit timer/event counter mode is selected. The count clocks are selected with bits 0 to 3 (TCL10 to TCL13) of timer clock select register (TCL1). The overflow signal of 8-bit timer/event counter 1 (TM1) becomes a count clock of 8-bit timer/event counter 2 (TM2). Count operation enable/disable is selected with bit 0 (TCE1) of TMC1. (1) Interval timer operation The 8-bit timer/event counter operates as interval timer which generates interrupt requests repeatedly at intervals of the count value preset to 2-channel 8-bit compare registers (CR10 and CR20). When setting the count value, the upper 8-bit value is set as CR20 and the lower 8-bit value as CR10. For the count value (interval time) which can be set refer to Table 9-9. When the 8-bit timer register 1 (TM1) and CR10 values match and the 8-bit timer register 2 (TM2) and CR20 values match, counting continues with the TM1 and TM2 values cleared to 0 and the interrupt request signal (INTTM2) is generated. For the operation timings of the interval timer, refer to Figure 9-11. Count clock can be selected with bits 0 to 3 (TCL10 to TCL13) of the timer clock select register 1 (TCL1). The overflow signal of the TM1 becomes a count clock of the TM2.
Figure 9-11. Interval Timer Operation Timings
t
Count Clock
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TMS (TM1, TM2) Count Value
0000
0001
N
0000 Clear N
0001
N
0000 0001 Clear N
N
Count Start CR10, CR20 N
N
INTTM2 Interrupt Request Acknowledge TO2 Interrupt Request Acknowledge
Interval Time
Interval Time
Interval Time
Remark
Interval time = (N + 1) x t : N = 0000H to FFFFH
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Caution
Even if the 16-bit timer/event counter mode is used, when the TM1 count value matches the CR10 value, interrupt request (INTTM1) is generated and the F/F of 8-bit timer/event counter output control circuit 1 is inverted. Thus, when using 8-bit timer/event counter as 16-bit interval timer, set the INTTM1 mask flag TMMK1 to 1 to disable INTTM1 acknowledgment. When reading 16-bit timer (TMS) count value, use the 16-bit memory manipulation instruction.
Table 9-9. Interval Times when 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2) are Used as 16-Bit Timer/Event Counter
TCL13 0 0 0 0 1 1 1 1 1 1 1 1 TCL12 0 0 1 1 0 0 0 0 1 1 1 1 TCL11 0 0 1 1 0 0 1 1 0 0 1 1 TCL10 0 1 0 1 0 1 0 1 0 1 0 1 Minimum Interval Time TI1 input cycle TI1 input cycle 2 x 1/fX (400 ns)
2
Maximum Interval Time 28 x TI1 input cycle 28 x TI1 input cycle 218 x 1/fX (26.2 ms) 219 x 1/fX (52.4 ms) 2
20
Resolution TI1 input edge cycle TI1 input edge cycle 22 x 1/fX (400 ns) 23 x 1/fX (800 ns) 24 x 1/fX (1.6 s) 25 x 1/fX (3.2 s) 26 x 1/fX (6.4 s) 27 x 1/fX (12.8 s) 28 x 1/fX (25.6 s) 29 x 1/fX (51.2 s) 210 x 1/fX (102.4 s) 212 x 1/fX (409.6 s)
23 x 1/fX (800 ns) 2 x 1/fX (1.6 s)
4
x 1/fX (104.9 ms) x 1/fX (419.4 ms) x 1/fX (1.7 s) x 1/fX (6.7 s)
25 x 1/fX (3.2 s) 2 x 1/fX (6.4 s)
6
221 x 1/fX (209.7 ms) 2
22
27 x 1/fX (12.8 s) 2 x 1/fX (25.6 s)
8
223 x 1/fX (838.9 ms) 2
24
29 x 1/fX (51.2 s) 2
10
225 x 1/fX (3.4 s) 2
26
x 1/fX (102.4 s)
212 x 1/fX (409.6 s) Setting prohibited
228 x 1/fX (26.8 s)
Other than above
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Remarks
1. 2. 3.
fX: Main system clock oscillation frequency TCL10 to TCL13: Bits 0 to 3 of the timer clock select register 1 (TCL1) Values in parentheses apply to operation with fX = 10.0 MHz.
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(2) External event counter operations The external event counter counts the number of external clock pulses to be input to the TI1/P33 pin with 2-channel 8-bit timer registers 1 and 2 (TM1 and TM2). TM1 is incremented each time the valid edge specified with the timer clock select register 1 (TCL1) is input. When TM1 overflows, TM2 is incremented with the overflow signal as the count clock. Either the rising or falling edge can be selected. When the TM1 and TM2 counted values match the values of 8-bit compare registers (CR10 and CR20), TM1 and TM2 are cleared to 0 and the interrupt request signal (INTTM2) is generated.
Figure 9-12. External Event Counter Operation Timings (with Rising Edge Specified)
TI1 Pin Input
TMS (TM1, TM2) Count Value
0000 0001 0002 0003 0004 0005
N-1
N
0000 0001 0002 0003
CR10, CR20
N
INTTM2
Caution Even if the 16-bit timer/event counter mode is used, when the TM1 count value matches the CR10
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value, interrupt request (INTTM1) is generated and the F/F of 8-bit timer/event counter output control circuit 1 is inverted. Thus, when using 8-bit timer/event counter as 16-bit interval timer, set the mask flag TMMK1 to 1 to disable INTTM1 acknowledgment. When reading 16-bit timer (TMS) count value, use the 16-bit memory manipulation instruction.
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(3) Square-wave output operation The 8-bit timer/event counter operates as a square wave with any selected frequency which is output at intervals of the value preset to 8-bit compare registers (CR10 and CR20). When setting the count value, the upper 8bit value is set as CR20 and the lower 8-bit value as CR10. The TO2/P32 pin output status is inverted at intervals of the count value preset to CR10 and CR20 by setting bit 4 (TOE2) of the 8-bit timer output control register (TOC1) to 1. This enables a square wave with any selected frequency to be output.
Table 9-10. Square-Wave Output Ranges when 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2) are Used as 16-Bit Tmer/Event Counter
TCL13 0 0 1 1 1 1 1 1 1 1 TCL12 1 1 0 0 0 0 1 1 1 1 TCL11 1 1 0 0 1 1 0 0 1 1 TCL10 0 1 0 1 0 1 0 1 0 1
2
Minimum Pulse Width 2 x 1/fX (400 ns) 23 x 1/fX (800 ns) 24 x 1/fX (1.6 s) 2 x 1/fX (3.2 s)
5
Maximum Pulse Width 2
18
Resolution 2 x 1/fX (400 ns)
2
x 1/fX (26.2 ms)
219 x 1/fX (52.4 ms) 220 x 1/fX (104.9 ms) 2
21
23 x 1/fX (800 ns) 24 x 1/fX (1.6 s) 25 x 1/fX (3.2 s) 26 x 1/fX (6.4 s) 27 x 1/fX (12.8 s) 28 x 1/fX (25.6 s) 29 x 1/fX (51.2 s) 210 x 1/fX (102.4 s) 212 x 1/fX (409.6 s)
x 1/fX (209.7 ms) x 1/fX (838.9 ms) x 1/fX (3.4 s) x 1/fX (26.8 s)
26 x 1/fX (6.4 s) 2 x 1/fX (12.8 s)
7
222 x 1/fX (419.4 ms) 2
23
28 x 1/fX (25.6 s) 2 x 1/fX (51.2 s)
9
224 x 1/fX (1.7 s) 2
25
210 x 1/fX (102.4 s) 2
12
226 x 1/fX (6.7 s) 2
28
x 1/fX (409.6 s)
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Remarks
1. 2. 3.
fX: Main system clock oscillation frequency TCL10 to TCL13: Bits 0 to 3 of the timer clock select register 1 (TCL1) Values in parentheses apply to operation with fX = 10.0 MHz.
Figure 9-13. Square-Wave Output Operation Timings
Count Clock TM1 TM2 CR10 CR20 TO2
00H 00H N M Interval Time 01H N N+1 FFH 00H 01H FFH 00H 02H FFH 00H 01H M-1 M N 00H 01H 00H
Count Start
Lebel Inversion Counter Clear
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9.5 Cautions on 8-Bit Timer/Event Counter Operating
(1) Timer start errors An error of one clock maximum may occur concerning the time required for a match signal to be generated after timer start. This is because 8-bit timer registers 1 and 2 (TM1 and TM2) are started asynchronously with the count pulse.
Figure 9-14. 8-Bit Timer Register Start Timings
Count Pulse
TM1, TM2 Count Value
00H
01H
02H
03H
04H
Timer Start
(2) 8-bit compare registers 1 and 2 sets The 8-bit compare registers (CR10 and CR20) can be set to 00H. Therefore, when the 8-bit compare register is used as event counter, one-pulse count operation can be carried out. When the 8-bit compare registers are used as 16-bit timer/event counter, write data to CR10 and CR20 after setting bit 0 (TCE1) of the 8-bit timer mode control register (TMC1) to 0 and stopping timer operation.
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Figure 9-15. External Event Counter Operation Timings
TI1, TI2 Input
CR10, CR20
00H
TM1, TM2 Count Value
00H
00H
00H
00H
TO1, TO2
Interrupt Request Flag
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(3) Operation after compare register change during timer count operation If the values after the 8-bit compare registers (CR10 and CR20) are changed are smaller than those of 8-bit timer registers (TM1 and TM2), TM1 and TM2 continue counting, overflow and then restart counting from 0. Thus, if the value after CR10 and CR20 (M) change is smaller than that before change (N), it is necessary to restart the timer after changing CR10 and CR20.
Figure 9-16. Timings after Compare Register Change during Timer Count Operation
Count Pulse
CR10, CR20 TM1, TM2 Count Value
N
M
X-1
X
FFH
00H
01H
02H
Remark
N>X>M
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CHAPTER 10
WATCH TIMER
CHAPTER 10
WATCH TIMER
10.1 Watch Timer Functions
The watch timer has the following functions. * Watch timer * Interval timer The watch timer and the interval timer can be used simultaneously. (1) Watch timer When the 32.768 kHz subsystem clock is used, a flag (WTIF) is set at 0.5 second or 0.25 second intervals. When the 8.38 MHz main system clock is used, a flag (WTIF) is set at 0.5 second or 0.25 second intervals. In addition, when the 4.19 MHz (Standard: 4.194304 MHz) main system clock is used, a flag (WTIF) is set at 0.5 second or 1 second intervals. When a frequency other than above is used, a flag (WTIF) is not set at 0.5/0.25 or 0.5/1.0 intervals. Caution When 8.38 MHz or 4.19 MHz frequency is used, a time interval has a little error. (2) Interval timer Interrupt requests (INTTM3) are generated at the preset time interval.
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Table 10-1. Interval Timer Interval Time
Interval Time 24 x 1/fW 25 x 1/fW 26 x 1/fW 2 x 1/fW
7
When operated at fX = 10.0 MHz 409.6 s 819.2 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms
When operated at fX = 8.38 MHz 489 s 978 s 1.96 ms 3.91 ms 7.82 ms 15.6 ms
When operated at fX = 4.19 MHz 978 s 1.96 ms 3.91 ms 7.82 ms 15.6 ms 31.3 ms
When operated at fXT = 32.768 kHz 488 s 977 s 1.95 ms 3.91 ms 7.81 ms 15.6 ms
28 x 1/fW 2 x 1/fW
9
Remarks
fX
: Main system clock oscillation frequency
fXT : Subsystem clock oscillation frequency fW : Watch timer clock frequency (fX/28 or fXT)
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10.2 Watch Timer Configuration
The watch timer consists of the following hardware.
Table 10-2. Watch Timer Configuration
Item Counter Control register 5 bits x 1 Timer clock select register 2 (TCL2) Watch timer mode control register (TMC2) Configuration
10.3 Watch Timer Control Registers
The following two types of registers are used to control the watch timer. * Timer clock select register 2 (TCL2) * Watch timer mode control register (TMC2) (1) Timer clock select register 2 (TCL2)(Refer to Figure 10-2.) This register sets the watch timer count clock. TCL2 is set with an 8-bit memory manipulation instruction. RESET input sets TCL2 to 00H. Remark Besides setting the watch timer count clock, TCL2 sets the watchdog timer count clock and buzzer
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output frequency.
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Figure 10-1. Watch Timer Block Diagram
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TMC21 Clear
Selector
fW
Prescaler fW 24 fW 25 fW 26 fW 27 fW 28 fW 29
Selector
fX/28
Selector
5-Bit Counter Clear
fW 214
INTWT
fXT
fW 213
Selector
INTTM3 CHAPTER 10
3
TCL24
TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 TMC20
WATCH TIMER
Timer Clock Select Register 2 Internal Bus
Watch Timer Mode Control Register
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WATCH TIMER
Figure 10-2. Timer Clock Select Register 2 Format
Symbol TCL2 7 6 5 4 3 0 2 1 0 Address FF42H When Reset 00H R/W R/W
TCL27 TCL26 TCL25 TCL24
TCL22 TCL21 TCL20
TCL22 TCL21 TCL20
Watchdog Timer Count Clock Selection
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
fX/24 (625 kHz) fX/25 (313 kHz) fX/26 (156 kHz) fX/27 (78.1 kHz) fX/28 (39.1 kHz) fX/29 (19.5 kHz) fX/210 (9.8 kHz) fX/212 (2.4 kHz)
TCL24 0 1
Watch Timer Count Clock Selection fX/28 (39.1 kHz) fXT (32.768 kHz)
TCL27 TCL26 TCL25 x 0 0 1 1 x 0 1 0 1
Buzzer Output Frequency Selection
0
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Buzzer output disable fX/210 (9.8 kHz) fX/211 (4.9 kHz) fX/212 (2.4 kHz) Setting prohibited
1 1 1 1
Caution
If data other than identical data is to be rewritten to TCL2, the timer operation must be stopped first.
Remarks
1. 2. 3. 4.
fX fXT x
: Main system clock oscillation frequency : Subsystem clock oscillation frequency : don't care
Values in parentheses apply to operation with fX = 10.0 MHz or fXT = 32.768 kHz.
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(2) Watch timer mode control register (TMC2) This register sets the watch timer operating mode, watch flag set time and prescaler interval time and enables/ disables prescaler and 5-bit counter operations. TMC2 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC2 to 00H.
Figure 10-3. Watch Timer Mode Control Register Format
Symbol TMC2 7 0 6 5 4 3 2 1 0 Address FF4AH When Reset 00H R/W R/W
TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 TMC20
TMC23 TMC20 Watch Flag Set Time Selection 0 1 0 1 1 0 214/fW (0.5 s) 213/fW (0.25 s) 25/fW (977 s) 24/fW (488 s)
TMC21 Prescaler Operation ControlNote 0 1 Clear after operation stops Operation enable
TMC22 5-Bit Counter Operation Control 0 1
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Clear after operation stops Operation enable
TMC26 TMC25 TMC24 Prescaler Interval Time Selection 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 24/fW (488 s) 25/fW (977 s) 26/fW (1.95 ms) 27/fW (3.91 ms) 28/fW (7.81 ms) 29/fW (15.6 ms) Setting prohibited
Other than above
Note
Do not frequently clear the prescaler when using the watch timer. 1. 2. fW: Watch timer clock frequency (fX/28 or fXT) Values in parentheses apply to operation with fW = 32.768 kHz.
Remarks
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10.4 Watch Timer Operations
10.4.1 Watch timer operation When the 32.768 kHz subsystem clock or 8.38 kHz main system clock is used, the timer operates as a watch timer with a 0.5 second or 0.25 second interval. In addition, when the 4.19 MHz main system clock is used, the timer can operate as a watch timer with a 0.5 second or 1 second interval. Caution When 8.38 MHz or 4.19 MHz frequency is used, the time interval is slightly off. When fX = 8.38 MHz frequency is used, 28 fX 222 8.38 x 106
x214 =
= 0.5005136... (second)
When fX = 4.19 MHz frequency is used, 28 fX 221 4.19 x 106
x213 =
= 0.5005136... (second)
When fXT = 32.768 MHz frequency is used, 1 fXT 214 32.768 x 103
x214 =
= 0.50000... (second)
When fX = 10.0 MHz frequency is used (not intended),
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28 fX
x214 =
222 10.0 x 106
= 0.4194304 (second)
The watch timer sets the interrupt request flag (WTIF) to 1 at the constant time interval. The standby state (STOP mode/HALT mode) can be cleared by setting WTIF to 1. When bit 2 (TMC22) of the watch timer mode control register (TMC2) is set to 0, the 5-bit counter is cleared and the count operation stops. For simultaneous operation of the interval timer, zero-second start can be achieved by setting TMC22 to 0 (maximum error: 15.6 ms when operated at fXT = 32.768 kHz).
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10.4.2 Interval timer operation The watch timer operates as interval timer which generates interrupt requests repeatedly at an interval of the preset count value. The interval time can be selected with bits 4 to 6 (TMC24 to TMC26) of the watch timer mode control register (TMC2).
Table 10-3. Interval Timer Interval Time
TMC26 TMC25 TMC24
Interval Time 24 x 1/fW 25 x 1/fW 26 x 1/fW 2 x 1/fW
7
When operated at fX = 10.0 MHz 409.6 s 819.2 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms
When operated at fX = 8.38 MHz 489 s 978 s 1.96 ms 3.91 ms 7.82 ms 15.6 ms
When operated at fX = 4.19 MHz 978 s 1.96 ms 3.91 ms 7.82 ms 15.6 ms 31.3 ms
When operated at fXT = 32.768 kHz 488 s 977 s 1.95 ms 3.91 ms 7.81 ms 15.6 ms
0 0 0 0 1 1
0 0 1 1 0 0
0 1 0 1 0 1
28 x 1/fW 2 x 1/fW
9
Other than above
Setting prohibited
Remarks
fX
: Main system clock oscillation frequency
fXT : Subsystem clock oscillation frequency fW : Watch timer clock frequency (fX/28 or fXT) TMC24 to TMC26: Bits 4 to 6 of the watch timer mode control register (TMC2)
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CHAPTER 11
WATCHDOG TIMER
CHAPTER 11
WATCHDOG TIMER
11.1 Watchdog Timer Functions The watchdog timer has the following functions. * Watchdog timer * Interval timer Caution Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (WDTM) (the watchdog timer and the interval timer cannot be used simultaneously). (1) Watchdog timer mode An inadvertent program loop is detected. Upon detection of the inadvertent program loop, a non-maskable interrupt request or RESET can be generated.
Table 11-1. Watchdog Timer Inadvertent Program Loop Detection Time
Inadvertent Program Loop Detection Time 212 x 1/fX 213 x 1/fX 214 x 1/fX
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When operated at fX = 10.0 MHz 409.6 s 819.2 s 1.64 ms 3.28 ms
Inadvertent Program Loop Detection Time 216 x 1/fX 217 x 1/fX 218 x 1/fX 2
20
When operated at fX = 10.0 MHz 6.55 s 13.1 s 26.2 ms 104.9 ms
2
15
x 1/fX
x 1/fX
Remark
fX: Main system clock oscillation frequency
(2) Interval timer mode Interrupt requests are generated at the preset time intervals.
Table 11-2. Interval Time
Interval Time 212 x 1/fX 213 x 1/fX 214 x 1/fX 2
15
When operated at fX = 10.0 MHz 409.6 s 819.2 s 1.64 ms 3.28 ms
Interval Time 216 x 1/fX 217 x 1/fX 218 x 1/fX 2
20
When operated at fX = 10.0 MHz 6.55 ms 13.1 ms 26.2 ms 104.9 ms
x 1/fX
x 1/fX
Remark
fX: Main system clock oscillation frequency
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11.2 Watchdog Timer Configuration The watchdog timer consists of the following hardware.
Table 11-3. Watchdog Timer Configuration
Item Control register Configuration Timer clock select register 2 (TCL2) Watchdog timer mode register (WDTM)
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Figure 11-1. Watchdog Timer Block Diagram
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Internal Bus
fX 24 fX 25 fX 26 fX 27
8-Bit Prescaler fX 28 fX 29 fX 210 fX 212 RUN Clear TMIF4 Control Circuit
TMMK4
Selector
INTWDT Maskable Interrupt Request
CHAPTER 11
8-Bit Counter
RESET INTWDT Non-Maskable Interrupt Request
3
WATCHDOG TIMER
TCL22 TCL21 TCL20
RUN WDTM4 WDTM3
Timer Clock Select Register 2 Internal Bus
Watchdog Timer Mode Register
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WATCHDOG TIMER
11.3 Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer. * Timer clock select register 2 (TCL2) * Watchdog timer mode register (WDTM) (1) Timer clock select register 2 (TCL2) This register sets the watchdog timer count clock. TCL2 is set with an 8-bit memory manipulation instruction. RESET input sets TCL2 to 00H. Remark Besides setting the watchdog timer count clock, TCL2 sets the watch timer count clock and buzzer output frequency.
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Figure 11-2. Timer Clock Select Register 2 Format
Symbol TCL2 7 6 5 4 3 0 2 1 0 Address FF42H When Reset 00H R/W R/W
TCL27 TCL26 TCL25 TCL24
TCL22 TCL21 TCL20
TCL22 TCL21 TCL20
Watchdog Timer Count Clock Selection
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
fX/24 (625 kHz) fX/25 (313 kHz) fX/26 (156 kHz) fX/27 (78.1 kHz) fX/28 (39.1 kHz) fX/29 (19.5 kHz) fX/210 (9.8 kHz) fX/212 (2.4 kHz)
TCL24 0 1
Watch Timer Count Clock Selection fX/28 (39.1 kHz) fXT (32.768 kHz)
TCL27 TCL26 TCL25 x 0 0 1 1 x 0 1 0 1
Buzzer Output Frequency Selection
0
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Buzzer output disable fX/210 (9.8 kHz) fX/211 (4.9 kHz) fX/212 (2.4 kHz) Setting prohibited
1 1 1 1
Caution
If data other than identical data is to be rewritten to TCL2, the timer operation must be stopped first.
Remarks
1. 2. 3. 4.
fX fXT x
: Main system clock oscillation frequency : Subsystem clock oscillation frequency : don't care
Values in parentheses apply to operation with fX = 10.0 MHz or fXT = 32.768 kHz.
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(2) Watchdog timer mode register (WDTM) This register sets the watchdog timer operating mode and enables/disables counting. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H.
Figure 11-3. Watchdog Timer Mode Register Format
Symbol WDTM <7> RUN 6 0 5 0 4 3 2 0 1 0 0 0 Address FFF9H When Reset 00H R/W R/W
WDTM4 WDTM3
WDTM4 WDTM3 Watchdog Timer Operating Mode SelectionNote 1 0 x Interval timer ModeNote 2 (Maskable interrupt request occurs upon generation of an overflow.) 1 0 Watchdog timer mode 1 (Non-maskable interrupt request occurs upon generation of an overflow.) 1 1 Watchdog timer mode 2 (Reset operation is activated upon generation of an overflow.)
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RUN 0 1
Watchdog Timer Operation SelectionNote 3 Count stop Counter is cleared and counting starts.
Notes
1. Once set to 1, WDTM3 and WDTM4 cannot be cleared to 0 by software. 2. Interval timer operation starts when the RUN bit is set to 1. 3. Once set to 1, RUN cannot be cleared to 0 by software. Thus, once counting starts, it can only be stopped by RESET input.
Cautions 1. 2.
When 1 is set in RUN so that the watchdog timer is cleared, the actual overflow time may be up to 0.5% shorter than the time set by timer clock select register 2 (TCL2). In watchdog timer mode 1 or 2, make sure that the interrupt request flag (TMIF4) is set to 0 before setting WDTM4 to 1. If WDTM4 is set to 1 while TMIF4 is set to 1, a non-maskable interrupt request occurs regardless of the contents in WDTM3.
Remark
x: don't care
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WATCHDOG TIMER
11.4 Watchdog Timer Operations 11.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to detect any inadvertent program loop. The watchdog timer count clock (inadvertent program loop detection time interval) can be selected with bits 0 to 2 (TCL20 to TCL22) of the timer clock select register 2 (TCL2). Watchdog timer starts by setting bit 7 (RUN) of WDTM to 1. After the watchdog timer is started, set RUN to 1 within the inadvertent program loop time interval to be set. The watchdog timer can be cleared and counting is started by setting RUN to 1. If RUN is not set to 1 and the inadvertent program loop detection time is past, system reset or a non-maskable interrupt request is generated according to the WDTM bit 3 (WDTM3) value. Watchdog timer can be cleared by setting RUN to 1. The watchdog timer continues operating in the HALT mode but it stops in the STOP mode. Thus, set RUN to 1 before the STOP mode is set, clear the watchdog timer and then execute the STOP instruction. Cautions 1. 2. The actual inadvertent program loop detection time may be shorter than the set time by a maximum of 0.5%. When the subsystem clock is selected for CPU clock, watchdog timer count operation is stopped.
Table 11-4. Watchdog Timer Inadvertent Program Loop Detection Time
TCL22 0
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TCL21 0 0 1 1 0 0 1 1
TCL20 0 1 0 1 0 1 0 1
Inadvertent Program Loop Detection Time 2
12
fX = 10.0 MHz 409.6 s 819.2 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms 26.2 ms 104.9 ms
x 1/fX x 1/fX x 1/fX x 1/fX
0 0 0 1 1 1 1
213 x 1/fX 2
14
215 x 1/fX 2
16
217 x 1/f 2
18
220 x 1/fX
Remark
fX: Main system clock oscillation frequency TCL20 to TCL22: Bits 0 to 2 of the timer clock select register 2 (TCL2)
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11.4.2 Interval timer operation The watchdog timer operates as an interval timer which generates interrupt requests repeatedly at intervals of a preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0. The count clock (or interval time) can be selected with bits 0 to 2 (TCL20 to TCL22) of the time clock select register (TCL2). When 1 is written into WDTM bit 7 (RUN), the interval timer operation starts. When the watchdog timer operated as interval timer, the interrupt mask flag (TMMK4) and priority specify flag (TMPR4) are validated and the maskable interrupt request (INTWDT) can be generated. Among maskable interrupt requests, the INTWDT default has the highest priority. The interval timer continues operating in the HALT mode but it stops in the STOP mode. Thus, set WDTM bit 7 (RUN) to 1 before the STOP mode is set, clear the interval timer and then execute the STOP instruction. Cautions 1. 2. 3. Once bit 4 (WDTM4) of WDTM is set to 1 (with the watchdog timer mode selected), the interval timer mode is not set unless RESET input is applied. The interval time just after setting with WDTM may be shorter than the set time by up to 0.5%. When the subsystem clock is selected for CPU clock, watchdog timer count operation is stopped.
Table 11-5. Interval Timer Interval Time
TCL22 0 0 0 0 1
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TCL21 0 0 1 1 0 0 1 1
TCL20 0 1 0 1 0 1 0 1
Interval Time 212 x 1/fX 213 x 1/fX 214 x 1/fX 2
15
fX = 10.0 MHz 409.6 s 819.2 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms 26.2 ms 104.9 ms
x 1/fX x 1/f
216 x 1/fX 2
17
1 1 1
218 x 1/fX 220 x 1/fX
Remark
fX: Main system clock oscillation frequency TCL20 to TCL22: Bits 0 to 2 of the timer clock select register 2 (TCL2)
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CHAPTER 12
CLOCK OUTPUT CONTROL CIRCUIT
CHAPTER 12
CLOCK OUTPUT CONTROL CIRCUIT
12.1 Clock Output Control Circuit Functions
The clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSI. Clocks selected with the timer clock select register 0 (TCL0) are output from the PCL/ P35 pin. Follow the procedure below to output clock pulses. (1) Select the clock pulse output frequency (with clock pulse output disabled) with bits 0 to 3 (TCL00 to TCL03) of TCL0. (2) Set the P35 output latch to 0. (3) Set bit 5 (PM35) of port mode register 3 (PM3) to 0 (set to output mode). (4) Set bit 7 (CLOE) of TCL0 to 1. Caution Remark Clock output cannot be used if P35 output latch is set to 1. When clock output enable/disable is switched, the clock output control circuit does not output pulses with small widths (See the mark
* in Figure 12-1).
Figure 12-1. Remote Controlled Output Application Example
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CLOE
PCL/P35 Pin Output
*
*
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CLOCK OUTPUT CONTROL CIRCUIT
12.2 Clock Output Control Circuit Configuration
The clock output control circuit consists of the following hardware.
Table 12-1. Clock Output Control Circuit Configuration
Item Control register Configuration Timer clock select register 0 (TCL0) Port mode register 3 (PM3)
Figure 12-2. Clock Output Control Circuit Block Diagram
fX/23 fX/24 Selector fX/25 fX/26 fX/27 fX/28 fXT 4 Synchronizing Circuit
PCL/P35
CLOE TCL03 TCL02 TCL01 TCL00
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P35 Output Latch
PM35 Port Mode Register 3
Timer Clock Select Register 0 Internal Bus
12.3 Clock Output Function Control Registers
The following two types of registers are used to control the clock output function. * Timer clock select register 0 (TCL0) * Port mode register 3 (PM3) (1) Timer clock select register 0 (TCL0) This register sets PCL output clock. TCL0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TCL0 to 00H. Remark Besides setting PCL output clock, TCL0 sets the 16-bit timer register count clock.
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Figure 12-3. Timer Clock Select Register 0 Format
Symbol TCL <7> 6 5 4 3 2 1 0 Address FF40H When Reset 00H R/W R/W
CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00
TCL03 TCL02 TCL01 TCL00
PCL Output Clock Selection
0 0 1 1 1 1 1
0 1 0 0 0 0 1
0 1 0 0 1 1 0
0 1 0 1 0 1 0
fXT (32.768 kHz) fX/23 (1.25 MHz) fX/24 (625 kHz) fX/25 (313 kHz) fX/26 (156 kHz) fX/27 (78.1 kHz) fX/28 (39.1 kHz) Setting prohibited
Other than above
TCL06 TCL05 TCL04
16-bit Timer Register Count Clock Selection
0 0 0 1
0 1 1 0
0 0 1 0
TI0 (Valid edge specifiable) fX/2 (5.0 MHz) fX/22 (2.5 MHz) fX/23 (1.25 MHz) Setting prohibited
Other than above
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CLOE 0 1
PCL Output Control Output disable Output enable
Cautions 1.
Setting of the TI0/INTP0 pin valid edge is performed by external interrupt mode register (INTM0), and selection of the sampling clock frequency is performed by the sampling clock selection register (SCS).
2. 3. 4.
When enabling PCL output, set TCL00 to TCL03, then set 1 in CLOE with a 1-bit memory manipulation instruction. To read the count value when TI0 has been specified as the TM0 count clock, the value should be read from TM0, not from the 16-bit capture register (CR01). If data other than identical data is to be rewritten to TCL0, the timer operation must be stopped first.
Remarks
1. 2. 3. 4. 5.
fX fXT
: Main system clock oscillation frequency : Subsystem clock oscillation frequency
TI0 : 16-bit timer/event counter input pin TM0 : 16-bit timer register Values in parentheses apply to operation with fX = 10.0 MHz or fXT = 32.768 kHz.
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(2) Port mode register 3 (PM3) This register sets port 3 input/output in bit-wise. When using the P35/PCL pin for clock output function, set PM35 and output latch of P35 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH.
Figure 12-4. Port Mode Register 3 Format
Symbol PM3
7 PM37
6 PM36
5 PM35
4 PM34
3 PM33
2 PM32
1 PM31
0 PM30
Address FF23H
When Reset 00H
R/W R/W
PM3n
P3n Pin Input/Output Mode Selection (n = 0 to 7)
0 1
Output mode (output buffer ON) Input mode (output buffer OFF)
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CHAPTER 13
BUZZER OUTPUT CONTROL CIRCUIT
CHAPTER 13
BUZZER OUTPUT CONTROL CIRCUIT
13.1 Buzzer Output Control Circuit Functions
The buzzer output control circuit outputs a square wave with a frequency of either 2.4 kHz, 4.9 kHz, or 9.8 kHz. The buzzer frequency selected with timer clock select register 2 (TCL2) is output from the BUZ/P36 pin. Follow the procedure below to output the buzzer frequency. (1) Select the buzzer output frequency with bits 5 to 7 (TCL25 to TCL27) of TCL2. (2) Set the P36 output latch to 0. (3) Set bit 6 (PM36) of port mode register 3 (PM3) to 0 (Set to output mode). Caution Buzzer output cannot be used if P36 output latch is set to 1.
13.2 Buzzer Output Control Circuit Configuration
The buzzer output control circuit consists of the following hardware.
Table 13-1. Buzzer Output Control Circuit Configuration
Item Control register Configuration Timer clock select register 2 (TCL2) Port mode register 3 (PM3)
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Figure 13-1. Buzzer Output Control Circuit Block Diagram
fX/211 fX/212
Selector
fX/210
BUZ/P36
3
TCL27 TCL26 TCL25 Timer Clock Select Register 2
P36 Output Latch
PM36 Port Mode Register 3
Internal Bus
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BUZZER OUTPUT CONTROL CIRCUIT
13.3 Buzzer Output Function Control Registers
The following two types of registers are used to control the buzzer output function. * Timer clock select register 2 (TCL2) * Port mode register 3 (PM3) (1) Timer clock select register 2 (TCL2) This register sets the buzzer output frequency. TCL2 is set with an 8-bit memory manipulation instruction. RESET input sets TCL2 to 00H. Remark Besides setting the buzzer output frequency, TCL2 sets the watch timer count clock and the watchdog timer count clock.
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BUZZER OUTPUT CONTROL CIRCUIT
Figure 13-2. Timer Clock Select Register 2 Format
Symbol TCL2 7 6 5 4 3 0 2 1 0 Address FF42H When Reset 00H R/W R/W
TCL27 TCL26 TCL25 TCL24
TCL22 TCL21 TCL20
TCL22 TCL21 TCL20
Watchdog Timer Count Clock Selection
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
fX/24 (625 kHz) fX/25 (313 kHz) fX/26 (156 kHz) fX/27 (78.1 kHz) fX/28 (39.1 kHz) fX/29 (19.5 kHz) fX/210 (9.8 kHz) fX/212 (2.4 kHz)
TCL24 0 1
Watch Timer Count Clock Selection fX/28 (39.1 kHz) fXT (32.768 kHz)
TCL27 TCL26 TCL25 x 0 0 1 1 x 0 1 0 1
Buzzer Output Frequency Selection
0
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Buzzer output disable fX/210 (9.8 kHz) fX/211 (4.9 kHz) fX/212 (2.4 kHz) Setting prohibited
1 1 1 1
Caution
If data other than identical data is to be rewritten to TCL2, the timer operation must be stopped first.
Remarks
1. 2. 3. 4.
fX fXT x
: Main system clock oscillation frequency : Subsystem clock oscillation frequency : don't care
Values in parentheses apply to operation with fX = 10.0 MHz or fXT = 32.768 kHz.
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(2) Port mode register 3 (PM3) This register sets port 3 input/output bit-wise. When using the P36/BUZ pin for buzzer output function, set PM36 and output latch of P36 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH.
Figure 13-3. Port Mode Register 3 Format
Symbol PM3 7 PM37 6 PM36 5 PM35 4 PM34 3 PM33 2 PM32 1 PM31 0 PM30 Address FF23H When Reset 00H R/W R/W
PM3n
P3n Pin Input/Output Mode Selection (n = 0 to 7)
0 1
Output mode (output buffer ON) Input mode (output buffer OFF)
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CHAPTER 14
A/D CONVERTER
CHAPTER 14
A/D CONVERTER
14.1 A/D Converter Functions
The A/D converter converts an analog input into a digital value. It consists of 8 channels (ANI0 to ANI7) with an 8-bit resolution. The conversion method is based on successive approximation and the conversion result is held in the 8-bit A/D conversion result register (ADCR). The following two ways are available to start A/D conversion. (1) Hardware start Conversion is started by trigger input (INTP3). (2) Software start Conversion is started by setting the A/D converter mode register (ADM). One channel of analog input is selected from ANI0 to ANI7 and A/D conversion is carried out. In the case of hardware start, A/D conversion operation stops when it terminates and an interrupt request (INTAD) is generated. In the case of software start, the A/D conversion operation is repeated. Each time an A/D conversion operation ends, an interrupt request (INTAD) is generated.
14.2 A/D Converter Configuration
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The A/D converter consists of the following hardware.
Table 14-1. A/D Converter Configuration
Item Analog input Control register Configuration 8 channels (ANI0 to ANI7) A/D converter mode register (ADM) A/D converter input select register (ADIS) Register Successive approximation register (SAR) A/D conversion result register (ADCR)
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Internal Bus 4 ANI0/P10 ANI1/P11 SelectorNote 1 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 INTP3/P03 Trigger Enable CS TRG
Figure 14-1.
A/D Converter Block Diagram
A/D Converter Input Selection Register
ADIS3 ADIS2 ADIS1 ADIS0
Series Resistor String AVDD Sample and Hold Circuit Voltage Comparator Tap Selector SelectorNote 2 3 ADM1 to ADM3 Falling Edge Detection Circuit FR1 AVREF CHAPTER 14
AVSS Successive Approximation Register
A/D CONVERTER
Control Circuit
INTAD
INTP3 3 FR0 ADM3 ADM2 ADM1
A/D Conversion Result Register (ADCR)
A/D Converter Mode Register Internal Bus
Notes
1. 2.
Selector to select the number of channels to be used for analog input Selector to select the channel for A/D conversion
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(1) Successive approximation register (SAR) This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string and holds the result from the most significant bit (MSB). When up to the least significant bit (LSB) is held (termination of A/D conversion), the SAR contents are transferred to the A/D conversion result register (ADCR). (2) A/D conversion result register (ADCR) This register holds the A/D conversion result. Each time A/D conversion terminates, the conversion result is loaded from the successive approximation register (SAR). ADCR is read with an 8-bit memory manipulation instruction. RESET input makes ADCR undefined. (3) Sample & hold circuit The sample & hold circuit samples each analog input signal sequentially applied from the input circuit and sends it to the voltage comparator. This circuit holds the sampled analog input voltage value during A/D conversion. (4) Voltage comparator The voltage comparator compares the analog input to the series resistor string output voltage. (5) Series resistor string The series resistor string is connected to among AVREF to AVSS and generates a voltage to be compared to the analog input. (6) ANI0 to ANI7 pins
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These are 8-channel analog input pins to input analog signals to undergo A/D conversion to the A/D converter. These pins except analog input pins selected with the A/D converter input select register (ADIS) can be used as the input/output port. Cautions 1. Use ANI0 to ANI7 input voltages within the specified range. If a voltage higher than AVREF or lower than AVSS is applied (even if within the absolute maximum ratings), the converted value of the corresponding channel will be undefined and may adversely affect the converted values of other channels. 2. Pins ANI0/P10 to ANI7/P17 The analog input pins ANI0 to ANI7 also function as input/output port (PORT1) pins. Pins used as the analog input should be specified to the input mode. When A/D conversion is performed with any of pins ANI0 to ANI7 selected, be sure not to execute a PORT1 input instruction while conversion is in progress, as this may reduce the conversion resolution. Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/D conversion, the expected A/D conversion value may not be obtainable due to coupling noise. Therefore, avoid applying pulses to pins adjacent to the pin undergoing A/D conversion.
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(7) AVREF pin This pin inputs the A/D converter reference voltage. It converts signals input to ANI0 to ANI7 into digital signals according to the voltage applied between AVREF and AVSS. If the voltage to be input to the AVREF pin is adjusted to the AVSS level in the standby mode, the current in the series resistor string will be decreased. Caution A series resistor string of approximately 10 k is connected between the AVREF pin and the AVSS pin. Therefore, if the output impedance of the reference voltage source is high, this will result in parallel connection to the series resistor string between the AVREF pin and the AVSS pin, and there will be a large reference voltage error. (8) AVSS pin Ground potential pin of the A/D converter. It must be at the same level as the VSS pin even if the A/D converter is not used. (9) AVDD pin Analog power supply pin of the A/D converter. It must be at the same level as the VDD pin even if the A/D converter is not used.
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14.3 A/D Converter Control Registers
The following two types of registers are used to control the A/D converter. * A/D converter mode register (ADM) * A/D converter input select register (ADIS) (1) A/D converter mode register (ADM) This register sets the analog input channel for A/D conversion, conversion time, conversion start/stop and external trigger. ADM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADM to 01H.
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Figure 14-2. A/D Converter Mode Register Format
Symbol ADM
<7> CS
<6> TRG
5 FR1
4 FR0
3 ADM3
2 ADM2
1 ADM1
0 1
Address FF80H
When Reset 01H
R/W R/W
ADM3 ADM2 ADM1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Analog Input Channel Selection ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7
FR1
FR0
A/D Conversion Time SelectionNote 1 When operated at fX = 10.0 MHz When operated at fX = 8.38 MHz 19.1 s Setting prohibitedNote 2 23.9 s When operated at fX = 4.19 MHz 38.1 s 19.1 s 47.7 s
0 0 1 1
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0 1 0 1
160/fX 80/fX 200/fX Setting prohibited
Setting prohibitedNote 2 Setting prohibitedNote 2 20.0 s
TRG 0 1
External Trigger Selection No external trigger (software starts mode) Conversion started by external trigger (hardware starts mode)
CS 0 1
A/D Conversion Operation Control Operation stop Operation start
Notes
1. 2.
Set so that the A/D conversion time is 19.1 s or more. Setting prohibited because A/D conversion time is less than 19.1 s. Set bit 0 to 1. To reduce power dissipation in the A/D converter when standby functions used, the bit 7 (CS) should be cleared to 0 to stop the A/D conversion operation before executing a HALT or STOP instruction. 3. To restart the stopped A/D conversion operation, the interrupt request flag (ADIF) should be cleared to 0 before starting the A/D conversion operation.
Cautions 1. 2.
Remark
fX: Main system clock oscillation frequency
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(2) A/D converter input select register (ADIS) This register determines whether the ANI0/P10 to ANI7/P17 pins should be used for analog input channels or ports. The pins which are not selected for analog input pins can be used as the input/output port. ADIS is set with an 8-bit memory manipulation instruction. RESET input sets ADIS to 00H. Cautions 1. Set the analog input channel in the following order. (1) Set the number of analog input channels with ADIS. (2) Using the A/D converter mode register (ADM), select one channel to undergo A/D conversion among the channels which is set for analog input with ADIS. 2. On-chip pull-up resistor is not used for the channels set for analog input with ADIS, irrespective of the value of bit 1 (PUO1) of the pull-up resistor option register.
Figure 14-3. A/D Converter Input Select Register Format
Symbol ADIS
7 0
6 0
5 0
4 0
3
2
1
0
Address FF84H
When Reset 00H
R/W R/W
ADIS3 ADIS2 ADIS1 ADIS0
ADIS3 ADIS2 ADIS1 ADIS0
Number of Analog Input Channel Selection
0
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0
0
0
No analog input channel (P10 to P17)
0
0
0
1
1 channel (ANI0, P11 to P17)
0
0
1
0
2 channels (ANI0, ANI1, P12 to P17)
0
0
1
1
3 channels (ANI0 to ANI2, P13 to P17)
0
1
0
0
4 channels (ANI0 to ANI3, P14 to P17)
0
1
0
1
5 channels (ANI0 to ANI4, P15 to P17)
0
1
1
0
6 channels (ANI0 to ANI5, P16, P17)
0
1
1
1
7 channels (ANI0 to ANI6, P17)
1
0
0
0
8 channels (ANI0 to ANI7)
Other than above
Setting prohibited
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14.4 A/D Converter Operations
14.4.1 Basic operations of A/D converter (1) Set the number of analog input channels with A/D converter input select register (ADIS). (2) From among the analog input channels set with ADIS, select one channel for A/D conversion with A/D converter mode register (ADM). (3) Sample the voltage input to the selected analog input channel with the sample & hold circuit. (4) Sampling for the specified period of time sets the sample & hold circuit to the hold state so that the circuit holds the input analog voltage until termination of A/D conversion. (5) Bit 7 of successive approximation register (SAR) is set and the tap selector sets the series resistor string voltage tap to (1/2) AVREF. (6) The voltage difference between the series resistor string voltage tap and analog input is compared with a voltage comparator. If the analog input is larger than (1/2) AVREF, the MSB of SAR remains set. If the input is smaller than (1/2) AVREF, the MSB is reset. (7) Next, bit 6 of SAR is automatically set and the operation proceeds to the next comparison. In this case, the series resistor string voltage tap is selected according to the preset value of bit 7 as described below. * * Bit 7 = 1: (3/4) AVREF Bit 7 = 0: (1/4) AVREF
The voltage tap and analog input voltage are compared and bit 6 of SAR is manipulated with the result as follows. * *
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Analog input voltage Voltage tap: Bit 6 = 1 Analog input voltage Voltage tap: Bit 6 = 0
(8) Comparison of this sort continues up to bit 0 of SAR. (9) Upon completion of the comparison of 8 bits, any resulting effective digital value remains in SAR and the resulting value is transferred to and latched in the A/D conversion result register (ADCR). At the same time, the A/D conversion termination interrupt request (INTAD) can also be generated.
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Figure 14-4. A/D Converter Basic Operation
Conversion Time Sampling Time A/D Converter Operation
Sampling
A/D Conversion
SAR
Undefined
80H
C0H or 40H
Conversion Result Conversion Result
ADCR
INTAD
A/D conversion operations are performed continuously until bit 7 (CS) of the A/D converter mode register (ADM) is reset (0) by software. If a write to the ADM is performed during an A/D conversion operation, the conversion operation is initialized, and if the CS bit is set (1), conversion starts again from the beginning. After RESET input, the value of ADCR is undefined.
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14.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion result (the value stored in the A/D conversion result register (ADCR)) is expressed by the following expression. ADCR = INT( VIN AVREF x 256 + 0.5)
or (ADCR - 0.5) x AVREF 256 VIN < (ADCR + 0.5) x AVREF 256
where
INT ( ) : Function which returns integer parts of value in parentheses. VIN AVREF ADCR : Analog input voltage : AVREF pin voltage : A/D conversion result register (ADCR) value
Figure 14-5 shows the relationship between the analog input voltage and the A/D conversion result.
Figure 14-5.
Relationship between Analog Input Voltage and A/D Conversion Result
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254
253 A/D Conversion Results (ADCR) 3
2
1
0
1 1 3 2 5 3 512 256 512 256 512 256
507 254 509 255 511 512 256 512 256 512
1
Input Voltage/AVREF
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14.4.3 A/D converter operating mode The operating mode is a select mode. One analog input channel is selected from among ANI0 to ANI7 with the A/D converter input select register (ADIS) and A/D converter mode register (ADM) and start the A/D conversion. The following two ways are available to start A/D conversion. * Hardware start: Conversion is started by trigger input (INTP3). * Software start: Conversion is started by setting ADM. The A/D conversion result is stored in the A/D conversion result register (ADCR) and the interrupt request signal (INTAD) is simultaneously generated. (1) A/D conversion by hardware start When bit 6 (TRG) and bit 7 (CS) of A/D converter mode register (ADM) are set to 1, the A/D conversion standby state is set. When the external trigger signal (INTP3) is input, the A/D conversion starts on the voltage applied to the analog input pins specified with bits 1 to 3 (ADM1 to ADM3) of ADM. Upon termination of the A/D conversion, the conversion result is stored in the A/D conversion result register (ADCR) and the interrupt request signal (INTAD) is generated. After one A/D conversion operation is started and terminated, another operation is not started until a new external trigger signal is input. If data with CS set to 1 is written to ADM again during A/D conversion, the converter suspends its A/D conversion operation and waits for a new external trigger signal to be input. When the external trigger input signal is reinput, A/D conversion is carried out from the beginning. If data with CS set to 0 is written to ADM during A/D conversion, the A/D conversion operation stops immediately.
Figure 14-6. A/D Conversion by Hardware Start
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INTP3 ADM Rewrite CS = 1, TRG = 1 ADM Rewrite CS = 1, TRG = 1
A/D Conversion
Standby State
ANIn
ANIn
Standby State
ANIn
Standby State
ANIm
ANIm
ANIm
ADCR
ANIn
ANIn
ANIn
ANIm
ANIm
INTAD
Remark
n = 0, 1, ..., 7 m = 0, 1, ..., 7
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(2) A/D conversion by software start When bit 6 (TRG) and bit 7 (CS) of the A/D converter mode register (ADM) are set to 0 and 1, respectively, A/D conversion starts on the voltage applied to the analog input pins specified with bits 1 to 3 (ADM1 to ADM3) of ADM. Upon termination of A/D conversion, the conversion result is stored in the A/D conversion result register (ADCR) and the interrupt request signal (INTAD) is generated. After one A/D conversion operation is started and terminated, the next A/D conversion operation starts immediately. The A/D conversion operation continues repeatedly until new data is written to ADM. If data with CS set to 1 is written to ADM again during A/D conversion, the converter suspends its A/D conversion operation and starts A/D conversion on the newly written data. If data with CS set to 0 is written to ADM during A/D conversion, the A/D conversion operation stops immediately.
Figure 14-7. A/D Conversion by Software Start
Conversion Start CS = 1, TRG = 0
ADM Rewrite CS = 1, TRG = 0
ADM Rewrite CS = 0, TRG = 0
A/D Conversion
ANIn
ANIn
ANIn
ANIm
ANIm
Conversion suspended Conversion results are not stored
Stop
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ADCR
ANIn
ANIn
ANIm
INTAD
Remark
n
= 0, 1, ..., 7
m = 0, 1, ..., 7
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14.5 Cautions on A/D Converter
(1) Current consumption in standby mode The A/D converter operates on the main system clock. Therefore, its operation stops in STOP mode or in HALT mode with the subsystem clock. As a current still flows in the AVREF pin at this time, this current must be cut in order to minimize the overall system power dissipation. In this example, the power dissipation can be reduced if a low level is output to the output port in the standby mode. However, the actual AVREF voltage is not so accurate and, accordingly, the converted value is not accurate and should be used for relative comparison only.
Figure 14-8. Example of Method of Reducing Power Dissipation in Standby Mode
VDD
Output Port
AVREF AVREF = VDD Series Resistor String
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AVSS
PD78014, 78014Y
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(2) Input range of ANI0 to ANI7 The input voltages of ANI0 to ANI7 should be within the specification range. In particular, if a voltage above AVREF or below AVSS is input (even if within the absolute maximum rating range), the conversion value for that channel will be indeterminate. The conversion values of the other channels may also be affected. (3) Noise countermeasures In order to maintain 8-bit resolution, attention must be paid to noise on pins AVREF and ANI0 to ANI7. Since the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor is connected externally as shown in Figure 14-9 in order to reduce noise.
Figure 14-9. Analog Input Pin Disposition
If there is a possibility that a noise level of AVREF or higher or AVSS or lower may enter, clamp with a small diode with VF (0.3 V or less). AVREF ANI0 to ANI7 VDD C = 100 to 1000 pF VDD
Reference Voltage Input
AVDD AVSS
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VSS
(4) Pins ANI0/P10 to ANI7/P17 The analog input pins ANI0 to ANI7 also function as input/output port (PORT1) pins. Pins used as the analog input should be specified to the input mode. When A/D conversion is performed with any of pins ANI0 to ANI7 selected, be sure not to execute a PORT1 input instruction while conversion is in progress, as this may reduce the conversion resolution. Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/D conversion, the expected A/D conversion value may not be obtainable due to coupling noise. Therefore, avoid applying pulses to pins adjacent to the pin undergoing A/D conversion. (5) AVREF pin input impedance A series resistor string of approximately 10 k is connected between the AVREF pin and the AVSS pin. Therefore, if the output impedance of the reference voltage source is high, this will result in parallel connection to the series resistor string between the AVREF pin and the AVSS pin, and there will be a large reference voltage error.
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(6) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the A/D converter mode register (ADM) is changed. Caution is therefore required since, if a change of analog input pin is performed during A/D conversion, the A/ D conversion result and ADIF for the pre-change analog input may be set just before the ADM rewrite, and when ADIF is read immediately after the ADM rewrite, ADIF may be set despite the fact that the A/D conversion for the post-change analog input has not ended. (Refer to Figure 14-10.) When the A/D conversion is stopped, the ADIF must be cleared before restarting.
Figure 14-10. A/D Conversion End Interrupt Request Generation Timing
Rewriting ADM (ANln conversion starts)
Rewriting ADM (ANlm conversion starts)
ADIF is set, but conversion of ANlm is not completed
A/D conversion
ANIn
ANIn
ANIm
ANIm
ADCR
ANIn
ANIn
ANIm
ANIm
INTAD
(7) AVDD pin
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The AVDD pin is the analog circuit power supply pin, and supplies power to the input circuits of ANI0/P10 to ANI7/P17. Therefore, be sure to apply the voltage at the same level as VDD as shown in Figure 14-11, even in an application where the power supply is switched to the back-up power supply.
Figure 14-11. AVDD Pin Connection
AVREF
VDD Main Power Supply AVDD Back up Capacitor VSS AVSS
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[MEMO]
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SERIAL INTERFACE CHANNEL 0 (PD78014 Subseries)
CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78014 Subseries)
The PD78014 Subseries incorporates two channels of clock synchronous serial interfaces. Differences between channels 0 and 1 are as follows (Refer to CHAPTER 17 SERIAL INTERFACE CHANNEL 1 for details of the serial interface channel 1).
Table 15-1. Differences between Channels 0 and 1
Serial Transfer Mode 3-wire serial I/O Clock selection Transfer method fX/2
2 Note 3
Channel 0
4 5 6 7 8 9
Channel 1
, fX/2 , fX/2 , fX/2 , fX/2 , fX/2 , fX/2 , fX/2 , external clock, TO2 output MSB/LSB switchable as the start bit Automatic transmit/receive function
MSB/LSB switchable as the start bit
Transfer end flag
Serial interface channel 0 transfer end interrupt request flag (CSIIF0)
Serial interface channel 1 transfer end interrupt request flag (CSIIF1 and TRF) None
SBI (serial bus interface) 2-wire serial I/O
Use possible
Note
Can be set only when the main system clock oscillates at 4.19 MHz or less.
Differences of Serial interface channel 0 modes are shown in Table 15-2.
Table 15-2. Difference of Serial Interface Channel 0 Modes
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Operation mode 3-wire serial I/O
Used pin SCK0, SO0, SI0
Features * Input and output lines are independent and they can transfer/receive at the same time, so the data transfer processing time is fast. * NEC single-chip microcontrollers provide as before.
Usage Serial interface as is the case with the 75X/XL, 78K and 17K Series.
SBI mode
SCK0, SB0 or SB1
* Enables to configure serial bus with two signal lines, thus, even when connect to some microcontrollers, the number of ports can be cut and reduced the wiring and drawing around on a board. * High-speed serial interface to be complianced with the NEC standard bus format. * Address and command information onto the serial bus
2-wire serial I/O
SCK0, SB0 or SB1
* Enables to configure serial bus with two signal lines, thus, even when connect to some microcontrollers, the number of ports can be cut and reduced the wiring and drawing around on a board. * Enables to cope with any data transfer format by program.
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15.1 Serial Interface Channel 0 Functions
Serial interface channel 0 employs the following four modes. * Operation stop mode * 3-wire serial I/O mode * SBI (serial bus interface) mode * 2-wire serial I/O mode Caution Do not switch the operation mode (3-wire serial I/O/2-wire serial I/O/SBI) during the serial interface channel 0 operation enable. The operation mode should be switched after stopping the serial operation. (1) Operation stop mode This mode is used when serial transfer is not carried out. Power dissipation can be reduced. (2) 3-wire serial I/O mode (MSB-/LSB-first selectable) This mode is used to 8-bit data transfer using three lines, one each for serial clock (SCK0), serial output (SO0) and serial input (SI0). This mode enables simultaneous transmission/reception and therefore reduces the data transfer processing time. The start bit of transferred 8-bit data is switchable between MSB and LSB, so that devices can be connected regardless of their start bit recognition. This mode should be used when connecting with peripheral I/O devices or display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K series.
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(3) SBI (serial bus interface) mode (MSB-first) This mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (SCK0) and serial data bus (SB0 or SB1) (See Figure 15-1). The SBI mode complies with the NEC serial bus format and distinguishes the transfer data into "address", "command", and "data" to transmit or receive the data. * Address * Data : Data to select objective devices in serial communication : Data to be actually transferred
* Command : Data to instruct objective devices
In the actual transfer, the master device first outputs the "address" to the serial bus, and selects the slave device as communication target from among two or more devices. The serial transfer is then performed by transmitting and receiving "command" and "data" between the master and slave devices. The receiver automatically distinguishes the received data into "address", "command", or "data", by hardware. This function enable to use input/output ports effectively and to simplify a serial interface controller of application programs. In addition, wake-up function for handshake, acknowledge signal, and busy signal output function can be used.
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Figure 15-1. Serial Bus Interface (SBI) System Configuration Example
VDD Master CPU Slave CPU1
SCK0 SB0
SCK0 SB0
Slave CPU2
SCK0 SB0
Slave CPUn
SCK0
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SB0
(4) 2-wire serial I/O mode (MSB-first) This mode is used for 8-bit data transfer using two lines of serial clock (SCK0) and serial data bus (SB0 or SB1). This mode enables to cope with any one of the possible data transfer formats by controlling the SCK0 level and the SB0 or SB1 output level. Thus, the handshake line previously necessary for connection of two or more devices can be removed, resulting in an increased number of available input/output ports.
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Figure 15-2. Serial Bus Configuration Example with 2-Wire Serial I/O
VDD VDD
Master CPU
Slave
SCK0
SCK0
SB0 (SB1)
SB0 (SB1)
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15.2 Serial Interface Channel 0 Configuration
Serial interface channel 0 consists of the following hardware.
Table 15-3. Serial Interface Channel 0 Configuration
Item Register Configuration Serial I/O shift register 0 (SIO0) Slave address register (SVA) Control register Timer clock select register 3 (TCL3) Serial operating mode register 0 (CSIM0) Serial bus interface control register (SBIC) Interrupt timing specify register (SINT) Port mode register 2 (PM2)Note
Note
Refer to Figure 6-6 P20, P21, P23 to P26 Block Diagrams (PD78014 Subseries) and Figure 6-7 P22 and P27 Block Diagrams (PD78014 Subseries).
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Serial Operating Mode Register 0
Control Circuit
Figure 15-3.
Serial Interface Channel 0 Block Diagram
Internal Bus Serial Bus Interface Control Register Slave Address Register (SVA) Match
BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
CSIM CSIE0 COI WUP CSIM CSIM CSIM CSIM 00 04 03 02 01
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SVAM
SI0/SB0/P25 PM25
Output Control
Selector
P25 Output Latch
Serial I/O Shift Register 0 (SIO0)
CLR SET D Q
SERIAL INTERFACE CHANNEL 0 (PD78014 Subseries)
SO0/SB1/P26 PM26
Output Control
Selector P26 Output Latch Bus Release/ Command/ Acknowledge Detector Serial Clock Counter
Output Control
ACKD CMDD RELD WUP
Busy/ Acknowledge Output Circuit
CLD SCK0/P27 PM27
Interrupt Request Signal Generator TO2
INTCSI0
Serial Clock Control Circuit CSIM00 CSIM01
P27 Output Latch
Selector
Selector
fX/22 to fX/29
CSIM00 CSIM01 CLD SIC SVAM
4
TCL33 TCL32 TCL31 TCL30 Timer Clock Select Register 3
Interrupt Timing Specification Register Internal Bus
Remark
Output control performs selection between CMOS output and N-ch open-drain output.
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SERIAL INTERFACE CHANNEL 0 (PD78014 Subseries)
(1) Serial I/O shift register 0 (SIO0) This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO0 is set with an 8-bit memory manipulation instruction. When bit 7 (CSIE0) of serial operating mode register 0 (CSIM0) is 1, writing data to SIO0 starts serial operation. In transmission, data written to SIO0 is output to the serial output (SO0) or serial data bus (SB0/SB1). In reception, data is read from the serial input (SI0) or SB0/SB1 to SIO0. The SBI mode and 2-wire serial I/O mode bus configurations enables the pin to serve for both input and output. Thus, in the case of a device for reception, write FFH to SIO0 in advance (except when address reception is carried out by setting bit 5 (WUP) of CSIM0 to 1). In the SBI mode, the busy state can be cleared by writing data to SIO0. In this case, bit 7 (BSYE) of the serial bus interface control register (SBIC) is not cleared to 0. RESET input makes SIO0 undefined. (2) Slave address register (SVA) This is an 8-bit register to set the slave address value for connection of a slave device to the serial bus. SVA is set with an 8-bit memory manipulation instruction. This register does not be used in the 3-wire serial I/O mode. The master device outputs a slave address for selection of a particular slave device to the connected slave device. These two data (the slave address output from the master device and the SVA value) are compared with an address comparator. If they match, the slave device has been selected. In that case, bit 6 (COI) of serial operating mode register 0 (CSIM0) becomes 1. Address comparison can also be executed on the data of LSB-masked high-order 7 bits when bit 4 (SVAM) of the interrupt timing specify register (SINT) is 1.
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If no matching is detected in address reception, bit 2 (RELD) of the serial bus interface control register (SBIC) is cleared to 0. In the SBI mode, when bit 5 (WUP) of CSIM0 is 1, the wake-up function is available. In this case, the interrupt request signal (INTCSI0) is generated only if the the slave address output from the master device matches the value of SVA. With this interrupt request, the slave device acknowledges that a communication request is sent from the master device. When bit 5 (SIC) of the interrupt timing specification register has been set to 1, the wakeup function is not available even if WUP is 1. (The interrupt request signal is generated at the bus release in the SBI mode) The SIC must be cleared to 0 while in use of the wake-up function. Further, when SVA transmits data as the master or slave device in the SBI mode or 2-wire serial I/O mode, SVA can be used to detect errors. RESET input makes SVA undefined.
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(3) SO0 latch This latch holds SI0/SB0/P25 and SO0/SB1/P26 pin levels. It can be directly controlled by software. In the SBI mode, this latch is set upon termination of the 8th serial clock. (4) Serial clock counter This counter counts the serial clocks to be output and input during transmission/reception and to check whether 8-bit data has been transmitted/received. (5) Serial clock control circuit This circuit controls serial clock supply to the serial I/O shift register 0 (SIO0). When the internal system clock is used, the circuit also controls clock output to the SCK0/P27 pin. (6) Interrupt request signal generator This circuit controls interrupt request signal generation. It generates the interrupt request signal in the following cases. * In the 3-wire serial I/O mode and 2-wire serial I/O mode This circuit generates an interrupt request signal every eight serial clocks. * In the SBI mode When WUPNote is 0 ...... Generates an interrupt request signal every eight serial clocks. When WUPNote is 1 ...... Generates an interrupt request signal when the serial I/O shift register 0 (SIO0) value matches the slave address register (SVA) value after address reception. Note
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WUP is a wake-up function specification bit. It is bit 5 of the serial operating mode register 0 (CSIM0). Bit 5 (SIC) of the interrupt timing select register (SINT) must be 0 when the wake-up function (WUP = 1) is selected.
(7) Busy/acknowledge output circuit and bus release/command/acknowledge detector These two circuits output and detect various control signals in the SBI mode. These do not operate in the 3-wire serial I/O mode and 2-wire serial I/O mode.
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15.3 Serial Interface Channel 0 Control Registers
The following four types of registers are used to control serial interface channel 0. * Timer clock select register 3 (TCL3) * Serial operating mode register 0 (CSIM0) * Serial bus interface control register (SBIC) * Interrupt timing specify register (SINT) (1) Timer clock select register 3 (TCL3) (See Figure 15-4.) This register sets the serial clock of serial interface channel 0. TCL3 is set with an 8-bit memory manipulation instruction. RESET input sets TCL3 to 88H. Remark TCL3 has functions to set the serial clock of serial interface channel 1 besides setting the serial clock of serial interface channel 0. (2) Serial operating mode register 0 (CSIM0) (See Figure 15-5.) This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop, wake-up function and displays the address comparator match signal. CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H. Caution Do not switch the operation mode (3-wire serial I/O/2-wire serial I/O/SBI) during the serial
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interface channel 0 operation enable. The operation mode should be switched after stopping the serial operation.
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Figure 15-4. Timer Clock Select Register 3 Format
Symbol TCL3
7
6
5
4
3
2
1
0
Address FF43H
When Reset 88H
R/W R/W
TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30
TCL33 TCL32 TCL31 TCL30
Serial Interface Channel 0 Serial Clock Selection
0 0 1 1 1 1 1 1
1 1 0 0 0 0 1 1
1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1
fX/22
Note
fX/23 (1.25 MHz) fX/24 (625 kHz) fX/25 (313 kHz) fX/26 (156 kHz) fX/27 (78.1 kHz) fX/28 (39.1 kHz) fX/29 (19.5 kHz) Setting prohibited
Other than above
TCL37 TCL36 TCL35 TCL34
Serial Interface Channel 1 Serial Clock Selection
0 0 1 1
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1 1 0 0 0 0 1 1
1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1
fX/22
Note
fX/23 (1.25 MHz) fX/24 (625 kHz) fX/25 (313 kHz) fX/26 (156 kHz) fX/27 (78.1 kHz) fX/28 (39.1 kHz) fX/29 (19.5 kHz) Setting prohibited
1 1 1 1
Other than above
Note
Can be set only when the main system clock oscillate at 4.19 MHz or less. If TCL3 is to be rewritten in data other than identical data, the timer operation must be stopped first. 1. fX: Main system clock oscillation frequency 2. Values in parentheses apply to operation with fX = 10.0 MHz.
Caution Remarks
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Figure 15-5. Serial Operating Mode Register 0 Format (1/2)
Symbol CSIM0 R/W <7> CSIE0 <6> COI <5> 4 3 2 1 0 Address FF60H When Reset 00H R/W R/WNote 1
WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection 0 1 1 x 0 1 Input clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
R/W
CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27 04 0 03 x 02 0 1 1 x 0 0 0 1
Operating Mode 3-wire serial I/O mode
Start Bit
SI0/SB0/P25 Pin Function
SO0/SBI/P26 Pin Function SO0 (CMOS output)
SCK0/P27 Pin Function SCK0 (CMOS input/output) SCK0
MSB LSB
SI0Note 2 (input)
Note 3 Note 3
SBI mode 0 0 0 1
MSB
P25 (CMOS input/output)
SB1
1
0
0
x
x
(N-ch open-drain (CMOS input/output) P26 input/output)
Note 3 Note 3
SB0 0 1
1
0
0
x
x
(N-ch open-drain (CMOS input/ input/output) output) SB1 SCK0
Note 3 Note 3
2-wire 0 0 0 1 serial I/O mode
MSB
P25 (CMOS input/output) SB0
1
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1
0
x
x
(N-ch open-drain (N-ch openinput/output) P26 drain input/output)
Note 3 Note 3
1
0
0
x
x
0
1
(N-ch open-drain (CMOS input/output) input/output)
R/W
WUP Wake-up Function ControlNote 4 0 1 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1) matches the slave address register (SVA) data in SBI mode
Notes
1. Bit 6 (COI) is a Read-Only bit. 2. Can be used as P25 (CMOS input) when used only for transmission. 3. Can be used freely as port function. 4. When the wake-up function is used (WUP = 1), bit 5 (SIC) of the interrupt timing select register (SINT) must be set to 0.
Remark
x
: don't care
PMxx: Port mode register Pxx : Output latch of port
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Figure 15-5. Serial Operating Mode Register 0 Format (2/2)
R
COI 0 1
Slave Address Comparison Result FlagNote Slave address register (SVA) not equal to serial I/O shift register 0 (SIO0) data Slave address register (SVA) equal to serial I/O shift register 0 (SIO0) data
R/W
CSIE0 0 1
Serial Interface Channel 0 Operation Control Operation stopped Operation enabled
Note
When CSIE0 = 0, COI becomes 0.
(3) Serial bus interface control register (SBIC) This register sets serial bus interface operation and displays status. SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H.
Figure 15-6. Serial Bus Interface Control Register Format (1/2)
Symbol SBIC <7> <6> <5> <4> <3> <2> <1> CMDT <0> RELT Address FF61H When Reset 00H R/W R/WNote
BSYE ACKD ACKE
ACKT CMDD RELD
R/W
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RELT
Use for bus release signal output. When RELT = 1, SO latch is set to 1. After SO latch setting, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
R/W
CMDT
Use for command signal output. When CMDT = 1, SO latch is cleared to (0). After SO latch clearance, automatically cleared to (0). Also cleared to (0) when CSIE0 = 0.
R
RELD
Bus Release Detection Set Conditions (RELD = 1) * When bus release signal (REL) is detected
Clear Conditions (RELD = 0) * When transfer start instruction is executed * If SIO0 and SVA values do not match in address reception * When CSIE0 = 0 * When RESET input is applied
Note
Bits 2, 3 and 6 (RELD, CMDD and ACKD) are Read-Only bits. CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0)
Remark
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Figure 15-6. Serial Bus Interface Control Register Format (2/2)
R
CMDD
Command Detection Set Conditions (CMDD = 1) * When command signal (CMD) is detected
Clear Conditions (CMDD = 0) * When transfer start instruction is executed * When bus release signal (REL) is detected * When CSIE0 = 0 * When RESET input is applied
R/W
ACKT
Acknowledge signal is output in synchronization with the falling edge of SCK0 clock immediately after execution of the instruction to be set to 1, and after acknowledge signal output, automatically cleared to 0. Also cleared to 0 upon start of serial interface transfer or when CSIE0 = 0
R/W
ACKE 0 1
Acknowledge Signal Output Control Acknowledge signal automatic output disable (output with ACKT enable) Before completion of transfer After completion of transfer Acknowledge signal is output in synchronization with the 9th clock falling edge of SCK0 (automatically output when ACKE = 1). Acknowledge signal is output in synchronization with the falling edge of SCK0 clock immediately after execution of the instruction to be set to 1 (automatically output when ACKE = 1). However, not automatically cleared to 0 after acknowledge signal output.
R
ACKD
Acknowledge Detection Set Conditions (ACKD = 1) * When acknowledge signal (ACK) is detected at the rising edge of SCK0 clock after completion of transfer
Clear Conditions (ACKD = 0)
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* At the falling edge of SCK0 immediately after the busy mode has been released when a transfer start instruction is executed * When CSIE0 = 0 * When RESET input is applied
R/W
BSYENote Synchronizing Busy Signal Output Control 0 Disables busy signal which is output in synchronization with the falling edge of SCK0 clock immediately after execution of the instruction to be cleared to 0. 1 Outputs busy signal at the falling edge of SCK0 clock following the acknowledge signal.
Note
Busy mode can be cleared by start of serial interface transfer. However, BSYE flag is not cleared to 0. 1. Zeros will be returned from bits 0, 1, and 4 (or RELT, CMDT, ACKT, respectively) if users read these bits after data setting is completed. 2. CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0)
Remarks
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(4) Interrupt timing specification register (SINT) This register sets the bus release interrupt and address mask functions and displays the SCK0/P27 pin level status. SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H.
Figure 15-7. Interrupt Timing Specification Register Format
Symbol SINT 7 0 <6> CLD <5> SIC <4> SVAM 3 0 2 0 1 0 0 0 Address FF63H When Reset 00H R/W R/WNote 1
R/W
SVAM 0 1
SVA Bit to be Used as Slave Address Bit 0 to Bit 7 Bit 1 to Bit 7
R/W
SIC 0
INTCSI0 Interrupt Factor SelectionNote 2 CSIIF0 is set (1) upon termination of serial channel 0 transfer
1
CSIIF0 is set (1) upon bus release detection termination of serial interface channel
R
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CLD 0 1
SCK0/P27 Pin LevelNote 3 Low Level High Level
Notes
1. Bit 6 (CLD) is a Read-Only bit. 2. When using wake-up function, set SIC to 0. 3. When CSIE0 = 0, CLD becomes 0.
Caution Remark
Be sure to set bit 0 to bit 3 to 0. SVA : Slave address register
CSIIF0: Interrupt request flag supports the INTCSI0 CSIE0 : Bit 7 of the serial operating mode register 0 (CSIM0)
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15.4 Serial Interface Channel 0 Operations
The following four operating modes are available to the serial interface channel 0. * Operation stop mode * 3-wire serial I/O mode * SBI mode * 2-wire serial I/O mode 15.4.1 Operation stop mode Serial transfer is not carried out in the operation stop mode. Thus, power dissipation can be reduced. The serial I/O shift register 0 (SIO0) does not carry out shift operation either and thus it can be used as normal 8-bit register. In the operation stop mode, the P25/SI0/SB0, P26/SO0/SB1 and P27/SCK0 pins can be used as normal input/ output ports. (1) Register setting The operation stop mode is set with the serial operating mode register 0 (CSIM0). CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H.
Symbol CSIM0
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<7> CSIE0
<6> COI
<5>
4
3
2
1
0
Address FF60H
When Reset 00H
R/W R/W
WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
R/W
CSIE0 0 1
Serial Interface Channel 0 Operation Control Operation stopped Operation enable
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15.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K series. Communication is carried out with three lines of serial clock (SCK0), serial output (SO0), and serial input (SI0). (1) Register setting The 3-wire serial I/O mode is set with the serial operating mode register 0 (CSIM0) and serial bus interface control register (SBIC). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H.
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Symbol CSIM0
<7> CSIE0
<6> COI
<5>
4
3
2
1
0
Address FF60H
When Reset 00H
R/W R/WNote 1
WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
R/W
CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection 0 1 1 x 0 1 Input clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
R/W
CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27 04 0 03 x 02 0 1 1 x 0 0 0 1
Operating Mode 3-wire serial I/O mode
Start Bit MSB LSB
SI0/SB0/P25 Pin Function SI0Note 2 (Input)
SO0/SBI/P26 Pin Function SO0 (CMOS output)
SCK0/P27 Pin Function SCK0 (CMOS input/output)
1 1
0 0
SBI mode (Refer to 15.4.3 SBI mode operation) 2-wire serial I/O mode (Refer to 15.4.4 2-wire serial I/O mode operation)
R/W
WUP 0 1
Wake-up Function ControlNote 3 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1) matches the slave address register (SVA) in SBI mode
R/W
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CSIE0 0 1
Serial Interface Channel 0 Operation Control Operation stopped Operation enable
Notes
1. Bit 6 (COI) is a Read-Only bit. 2. Can be used as P25 (CMOS input) when used only for transmission. 3. Be sure to set WUP to 0 when the 3-wire serial I/O mode is selected.
Remark
x
: don't care
PMxx: Port mode register Pxx : Output latch of port
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(b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H.
Symbol SBIC
<7>
<6>
<5>
<4>
<3>
<2>
<1> CMDT
<0> RELT
Address FF61H
When Reset 00H
R/W R/W
BSYE ACKD ACKE
ACKT CMDD RELD
R/W
RELT
When RELT = 1, SO latch is set to 1. After SO latch setting, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
R/W
CMDT
When CMDT = 1, SO latch is cleared to 0. After SO latch clearance, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0)
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(2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization of the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out at the falling edge of the serial clock (SCK0). The transmitted data is held in the SO0 latch and is output from the SO0 pin. The received data input to the SI0 pin is latched in SIO0 at the rising edge of SCK0. Upon termination of 8-bit transfer, SIO0 operation stops automatically and the interrupt request flag (CSIIF0) is set.
Figure 15-8. 3-Wire Serial I/O Mode Timings
SCK0
1
2
3
4
5
6
7
8
SI0
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
CSIIF0
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Transfer Start at the falling edge of SCK0
End of Transfer
The SO0 pin serves for CMOS output and generates the SO0 latch status. Thus, the SO0 pin output status can be manipulated by setting bit 0 (RELT) and bit 1 (CMDT) of the serial bus interface control register (SBIC). However, do not carry out this manipulation during serial transfer. The SCK0 pin output level is controlled by manipulating the P27 output latch in the output mode (internal system clock mode) (refer to 15.4.5 SCK0/P27 pin output manipulation).
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(3) Various signals Figure 15-9 shows RELT and CMDT operations.
Figure 15-9. RELT and CMDT Operations
SO0 Latch
RELT
CMDT
(4) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start at MSB or LSB. Figure 15-10 shows the configuration of the serial I/O shift register 0 (SIO0) and internal bus. As shown in the figure, MSB/LSB can be read/written in inverted form. MSB/LSB switching as the start bit can be specified with bit 2 (CSIM02) of the serial operating mode register 0 (CSIM0).
Figure 15-10. Circuit of Switching in Transfer Bit Order
7 6
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Internal Bus 1 0 LSB Start MSB Start Read/Write Gate Read/Write Gate
SO0 Latch SI0 Shift Register 0 (SIO0) D Q
SO0
SCK0
Start bit switching is realized by switching the bit order for data write to SIO0. The SIO0 shift order remains unchanged. Thus, switch the MSB/LSB start bit before writing data to the shift register.
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(5) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. * Serial interface channel 0 operation control bit (CSIE0) = 1 * Internal serial clock is stopped or SCK0 is the high level after 8-bit serial transfer. Caution If CSIE0 is set to "1" after data write to SIO0, transfer does not start. Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0) is set. 15.4.3 SBI mode operation SBI (Serial Bus Interface) is a high-speed serial interface in compliance with the NEC serial bus format. SBI has a format with the bus configuration function added to the clocked serial I/O method so that it can carry out communication with two or more devices with two signal conductors on the single-master high-speed serial bus. Thus, when making up a serial bus with two or more microcontrollers and peripheral ICs, the number of ports to be used and the number of wires on the board can be decreased. The master device can output to the serial data bus of the slave device "addresses" for selection of the serial communication target device, "commands" to instruct the target device and actual "data". The slave device can identify the received data into "address", "command" or "data", by hardware. This function enables the application program to control serial interface channel 0 to be simplified. The SBI function is incorporated into various devices including 75X/XL Series devices and 78K Series. Figure 15-11 shows a serial bus configuration example when a CPU having a serial interface compliant with SBI
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and peripheral ICs are used. In SBI, the SB0 (or SB1) serial data bus pin serves for open-drain output and so the serial data bus line is in wiredOR state. A pull-up resistor is necessary for the serial data bus line. Refer to (11) Cautions on SBI mode (d) described later when the SBI mode is used.
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Figure 15-11. Example of Serial Bus Configuration with SBI
VDD
SCK0 Master CPU SB0 (SB1)
Serial Clock Serial Data Bus
SCK0 SB0 (SB1)
Slave CPU Address 1
SCK0 SB0 (SB1)
Slave CPU Address 2
SCK0 SB0 (SB1)
Slave IC Address N
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Caution
When replacing the master CPU/slave CPU, a pull-up resistor is necessary for the serial clock line (SCK0) as well because serial clock line (SCK0) input/output switching is carried out asynchronously between the master and slave CPUs.
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(1) SBI functions In the conventional serial I/O method, when a serial bus is constructed by connecting two or more devices, many ports and wiring are necessary to distinguish chip select signals and command/data and to judge the busy state because only the data transfer function is available. If these operations are to be controlled by software, the software must be heavily loaded. In SBI, a serial bus can be constructed with two signal conductors of serial clock SCK0 and serial data bus SB0 (SB1). Thus, SBI is effective to decrease the number of microcontroller ports and that of wirings and routings on the board. The SBI functions are described below. (a) Address/command/data identify function Serial data is distinguished into addresses, commands and data. (b) Chip select function by address transmission The master executes slave chip selection by address transmission. (c) Wake-up function The slave can easily judge address reception (chip select judgment) with the wake-up function (which can be set/reset by software). When the wake-up function is set, the interrupt request signal (INTCSI0) is generated upon reception of a match address. Thus, when communication is executed with two or more devices, a CPU other than those of the selected slave devices can operate regardless of serial communication. (d) Acknowledge signal (ACK) control function
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The acknowledge signal to check serial data reception is controlled. (e) Busy signal (BUSY) control function The busy signal to report the slave busy state is controlled. (2) SBI definition The SBI serial data format and implication of signals to be used are defined as follows. Serial data to be transferred with SBI is distinguished into three types, "address", "command" and "data". Figure 15-12 shows the address, command and data transfer timings.
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Figure 15-12. SBI Transfer Timings
Address Transfer
SCK0
8
9
SB0 (SB1) Bus Release Signal
A7 Address Command Signal
A0
ACK
BUSY
Command Transfer
SCK0
9
SB0 (SB1)
C7 Command
C0 ACK
BUSY
READY
Data Transfer
SCK0
8
9
SB0 (SB1)
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D7 Data
D0 ACK
BUSY
READY
Remark
The broken line indicates the READY state. The bus release signal and the command signal are output by the master device. BUSY is output by the slave signal. ACK can be output by either the master or slave device (normally, the 8-bit data receiver outputs). Serial clocks continue to be output by the master device from 8-bit data transfer start to BUSY reset.
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(a) Bus release signal (REL) The bus release signal is generated when the SCK0 line is in high level (a serial clock is not output) and the SB0 (SB1) line changes from low level to high level. The bus release signal is output by the master.
Figure 15-13. Bus Release Signal
SCK0
"H"
SB0 (SB1)
The bus release signal indicates that the master will send the address to the slave. The slave contains hardware to detect the bus release signal. Caution The bus release signal is acknowledged when the SCK0 line is in high level, and the SB0 (SB1) line changes from low level to high level. Thus, if the timing at which bus changes deviates due to effects such as board capacity, it may be determined as the bus release signal even if data is sent. Therefore perform wiring carefully. (b) Command signal (CMD)
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The command signal is generated when the SCK0 line is in high level (a serial clock is not output) and the SB0 (SB1) line changes from high level to low level. The command signal is output by the master.
Figure 15-14. Command Signal
SCK0
"H"
SB0 (SB1)
The command signal indicates that the master will send the command to the slave (However, the command signal following the bus release signal indicates that address will be sent). The slave contains hardware to detect the command signal. Caution The command signal is acknowledged when the SCK0 line is in high level, and the SB0 (SB1) line changes from high level to low level. Thus, if the timing at which bus changes deviates due to effects such as board capacity, it may be determined as the command signal even if data is sent. Therefore perform wiring carefully.
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(c) Address The address is 8-bit data that the master outputs to the slave connected to the bus line to select a specific slave.
Figure 15-15. Address
SCK0 SB0 (SB1)
1 A7
2 A6
3 A5
4 A4
5 A3
6 A2
7 A1
8 A0
Address Bus Release Signal Command Signal
8-bit data following the bus release signal and the command signal is defined as the address. The slave detects the condition and checks by hardware if 8-bit data matches its specified number (the slave address). When 8-bit data matches the slave address, which means the slave is selected, the slave communicates with the master until the master instructs disconnection.
Figure 15-16. Slave Selection with Address
Master Slave 2 Address Transmission
Slave 1
Non-Selection
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Slave 2
Selection
Slave 3
Non-Selection
Slave 4
Non-Selection
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(d) Command and Data The master sends commands and sends/receives data to the slave selected by sending the address.
Figure 15-17. Command
SCK0 SB0 (SB1) 1 C7 2 C6 3 C5 4 C4 5 C3 6 C2 7 C1 8 C0
Command Signal
Command
Figure 15-18. Data
SCK0 SB0 (SB1)
1 D7
2 D6
3 D5
4 D4
5 D3
6 D2
7 D1
8 D0
Data
8-bit data following the command signal is defined as a command. 8-bit data wihtout the command signal is defined as data. How to use the command and data can be determined based on communication specifications.
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(e) Acknowledge signal (ACK) This signal is used between the sending side and receiving side devices for confirmation of correct serial data sending.
Figure 15-19. Acknowledge Signal (When output synchronously with SCK0 in 11th clock.)
SCK0 8 9 10 11
SB0 (SB1)
ACK
(When output synchronously with SCK0 in 9th clock.)
8 9
SCK0
SB0 (SB1)
ACK
Remark The broken line indicates the READY state.
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The acknowledge signal is a one-shot pulse synchronous with SCK0 falling, whose position can be synchronized with SCK0 in any clock. The sending side that has transferred 8-bit data checks if the acknowledge signal has been sent back by the receiving side. If this signal is not sent back by the slave device for a period after data sending, this means that the data sent has not been received correctly by the slave device.
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(f)
Busy signal (BUSY), Ready signal (READY) The busy signal informs the master that the slave is busy transmitting/receiving data. The ready signal informs the master that the slave is ready to transmit/receive data.
Figure 15-20. Busy Signal and Ready Signal
SCK0 8 9
SB0 (SB1)
ACK
BUSY
READY
Remark The broken line indicates the READY state. In the SBI mode, the slave informs the master of the busy state by setting the SB0 (SB1) line to low level. The busy signal is output following the acknowledge signal output by the slave. The busy signal is set/cleared synchronously with the falling edge of SCK0. The master terminates automatically to output the serial clock SCK0 when the busy signal is cleared. The master can start subsequent transmissions when the busy signal is cleared and changes to the ready state. Caution In the SBI mode, the BUSY signal is output until the falling of the next serial clock after the BUSY release indication. If WUP = 1 is set by mistake during this period, BUSY will not be released. Thus, after releasing BUSY, be sure to check that the SB0 (SB1) has become high level before setting WUP = 1.
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(3) Register setting The SBI mode is set with the serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC) and the interrupt timing specification register (SINT). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H.
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Symbol CSIM0 R/W
<7> CSIE0
<6> COI
<5>
4
3
2
1
0
Address FF60H
When Reset 00H
R/W R/WNote 1
WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection 0 1 1 x 0 1 Input clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
R/W
CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27 04 0 03 x 0 02
Operating Mode
Start Bit
SI0/SB0/P25 Pin Function
SO0/SB1/P26 Pin Function
SCK0/P27 Pin Function
3-wire serial I/O mode (Refer to 15.4.2 3-wire serial I/O mode operation)
Note 2 Note 2
SBI mode 0 0 0 1
MSB
P25 (CMOS input/output)
SB1
SCK0
1
0
x
x
(N-ch open-drain (CMOS input/output) P26 input/output)
Note 2 Note 2
SB0 0 1
1
0
0
x
x
(N-ch open-drain (CMOS input/ input/output) output)
1
1
2-wire serial I/O mode (Refer to 15.4.4 2-wire serial I/O mode operation)
R/W
WUP 0 1
Wake-up Function ControlNote 3 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1) matches the slave address register (SVA) data when SBI mode is used
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R
COI 0 1
Slave Address Comparison Result FlagNote 4 Slave address register (SVA) not equal to serial I/O shift register 0 (SIO0) data Slave address register (SVA) equal to serial I/O shift register 0 (SIO0) data
R/W
CSIE0 0 1
Serial Interface Channel 0 Operation Control Operation stopped Operation enable
Notes
1. Bit 6 (COI) is a Read-Only bit. 2. Can be used freely as port function. 3. When the wake-up function is used (WUP = 1), set bit 5 (SIC) of the interrupt timing specification register (SINT) to 0. 4. When CSIE0 = 0, COI becomes 0.
Remark
x
: don't care
PMxx: Port mode register Pxx : Output latch of port
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(b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H.
Symbol SBIC
<7>
<6>
<5>
<4>
<3>
<2>
<1> CMDT
<0> RELT
Address FF61H
When Reset 00H
R/W R/WNote
BSYE ACKD ACKE
ACKT CMDD RELD
R/W
RELT
Use for bus release signal output. When RELT = 1, SO latch is set to 1. After SO latch setting, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
R/W
CMDT
Use for command signal output. When CMDT = 1, SO latch is cleared to (0). After SO latch clearance, automatically cleared to (0). Also cleared to (0) when CSIE0 = 0.
R
RELD
Bus Release Detection Set Conditions (RELD = 1) * When bus release signal (REL) is detected
Clear Conditions (RELD = 0) * When transfer start instruction is executed * If SIO0 and SVA values do not match in address reception (only if WUP = 1) * When CSIE0 = 0 * When RESET input is applied
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R
CMDD
Command Detection Set Conditions (CMDD = 1) * When command signal (CMD) is detected
Clear Conditions (CMDD = 0) * When transfer start instruction is executed * When bus release signal (REL) is detected * When CSIE0 = 0 * When RESET input is applied
R/W
ACKT
Acknowledge signal is output in synchronization with the falling edge clock of SCK0 just after execution of the instruction to be set to 1, and after acknowledge signal output, automatically cleared to 0. Used as ACKE = 0 Also cleared to 0 upon start of serial interface transfer or when CSIE0 = 0. (continued)
Note
Bits 2, 3, and 6 (RELD, CMDD and ACKD) are Read-Only bits. 1. Zeros will be returned from bits 0, 1, and 4 (or RELT, CMDT, ACKT, respectively) if users read these bits after data setting is completed. 2. CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0)
Remarks
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(continued) R/W ACKE 0 1 Acknowledge Signal Automatic Output Control Acknowledge signal automatic output disable (output with ACKT enable) Before completion of transfer After completion of transfer Acknowledge signal is output in synchronization with the 9th clock falling edge of SCK0 (automatically output when ACKE = 1). Acknowledge signal is output in synchronization with the falling edge of SCK0 clock immediately after execution of the instruction to be set to 1 (automatically output when ACKE = 1). However, not automatically cleared to 0 after acknowledge signal output.
R
ACKD
Acknowledge Detection Set Conditions (ACKD = 1) * When acknowledge signal (ACK) is detected at the rising edge of SCK0 clock after completion of transfer
Clear Conditions (ACKD = 0) * At the falling edge of SCK0 clock immediately after the busy mode has been released when a transfer start instruction is executed * When CSIE0 = 0 * When RESET input is applied
R/W
BSYENote Synchronizing Busy Signal Output Control 0 Disables busy signal which is output in synchronization with the falling edge of SCK0 clock immediately after execution of the instruction to be cleared to (0) (with READY state). 1 Outputs busy signal at the falling edge of SCK0 clock following the acknowledge signal.
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Note
Busy mode can be cleared by start of serial interface transfer. However, the BSYE flag is not cleared to 0. CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0)
Remark
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(c) Interrupt timing specification register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H.
Symbol SINT
7 0
<6> CLD
<5> SIC
<4> SVAM
3 0
2 0
1 0
0 0
Address FF63H
When Reset 00H
R/W R/WNote 1
R/W
SVAM 0 1
SVA Bit to be Used as Slave Address Bits 0 to 7 Bits 1 to 7
R/W
SIC 0
INTCSI0 Interrupt Factor SelectionNote 2 CSIIF0 is set (1) upon termination of serial channel 0 transfer
1
CSIIF0 is set (1) upon bus release detection
R
CLD 0 1
SCK0/P27 Pin LevelNote 3 Low Level High Level
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Notes
1. Bit 6 (CLD) is a Read-Only bit. 2. When using wake-up function, set SIC to 0. 3. When CSIE0 = 0, CLD becomes 0.
Caution Remark
Be sure to set bits 0 to 3 to 0. SVA : Slave address register
CSIIF0: Interrupt request flag supports the INTCSI0 CSIE0 : Bit 7 of the serial operating mode register 0 (CSIM0)
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(4) Various signals Figures 15-21 to 15-26 show various signals in SBI and flag operations of the serial bus interface control register (SBIC). Table 15-4 lists various signals in SBI.
Figure 15-21. RELT, CMDT, RELD and CMDD Operations (Master)
Slave address write to SIO0 (Transfer Start Instruction) SIO0 SCK0
SB0 (SB1) RELT
CMDT
RELD
CMDD
Figure 15-22. RELD and CMDD Operations (Slave)
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Write FFH to SIO0 (Transfer start instruction)
Transfer start instruction
SIO0
A7
A6
A1
A0
SCK0
1
2
7
8
9 READY
SB0 (SB1)
A7
A6
A1
A0
ACK
Slave address When addresses match RELD When addresses do not match CMDD
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Figure 15-23. ACKT Operation
SCK0
6
7
8
9
SB0 (SB1)
D2
D1
D0
ACK
ACK signal is output a period of one clock immediately after setting
ACKT
When set during this period
Caution
Do not set ACKT before termination of transfer.
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Figure 15-24. ACKE Operations (a) When ACKE = 1 upon completion of transfer
SCK0 1 2 7 8 9
SB0 (SB1)
D7
D6
D2
D1
D0
ACK
ACK signal is output at 9th clock
ACKE When ACKE = 1 at this point
(b) When set after completion of transfer
SCK0 SB0 (SB1)
6
7
8
9
D2
D1
D0
ACK
ACK signal is output a period of one clock immediately after setting
ACKE
If set during this period and ACKE = 1 at the falling edge of the next SCK0
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(c) When ACKE = 0 upon completion of transfer
1 2 7 8 9
SCK0 SB0 (SB1)
D7
D6
D2
D1
D0
ACK signal is not output
ACKE When ACKE = 0 at this point
(d) When ACKE = 1 period is short
SCK0 SB0 (SB1) D2 D1 D0 ACK signal is not output
ACKE
If set and cleared during this period and ACKE = 0 at the falling edge of SCK0
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Figure 15-25. ACKD Operations (a) When ACK signal is output at 9th clock of SCK0
Transfer Start Instruction SIO0 Transfer Start SCK0 6 7 8 9
SB0 (SB1)
D2
D1
D0
ACK
ACKD
(b) When ACK signal is output after 9th clock of SCK0
Transfer Start Instruction SIO0 Transfer Start SCK0 6 7 8 9
SB0 (SB1)
D2
D1
D0
ACK
ACKD
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(c) Clear timing when transfer start is instructed in BUSY
Transfer Start Instruction SIO0
SCK0
6
7
8
9
SB0 (SB1)
D2
D1
D0
ACK
BUSY
D7
D6
ACKD
Figure 15-26. BSYE Operation
SCK0 6 7 8 9
SB0 (SB1)
D2
D1
D0
ACK
BUSY
BSYE
When BSYE = 1 at this point
Reset is performed during this period, and SB0 (SB1) changes when BSYE is 0 at the falling edge of SCK0.
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Signal Name Output Device Bus release signal (REL) Master SB0 (SB1) rising edge when SCK0 = 1 Definition Command signal (CMD) Master SB0 (SB1) falling edge when SCK0 = 1 Acknowledge signal (ACK) Master/ slave Low-level signal to be output to SB0 (SB1) during one-clock period of SCK0 after completion of serial reception Busy signal (BUSY) Slave [Synchronous BUSY signal] Low-level signal to be output to SB0 (SB1) following Acknowledge signal Ready signal (READY) Slave High-level signal to be output to SB0 (SB1) before serial transfer start and after completion of serial transfer
Table 15-4. Various Signals in SBI Mode (1/2)
Timing Chart
Output Condition
Effects on Flag
Meaning of Signal
* RELT set
SCK0 SB0 (SB1) "H"
* RELD set * CMDD clear
CMD signal is output to indicate that transmit data is an address. CHAPTER 15
* CMDT set
SCK0 SB0 (SB1) "H"
* CMDD set
i) Transmit data is an address after REL signal output. ii) REL signal is not output, and transmit data is a command.
SERIAL INTERFACE CHANNEL 0 (PD78014 Subseries)
<1> ACKE = 1 <2> ACKT set
* ACKD set
Completion of reception
[Synchronous BUSY output]
* BSYE = 1
--
Serial receive disable because of processing
SCK0 SB0 (SB1) D0
9 ACK BUSY READY
<1> BSYE = 0
ACK SB0 (SB1) D0 BUSY READY
--
Serial receive enable
<2> Execution of instruction data write SIO0 (trans start instruction)
Table 15-4. Various Signals in SBI Mode (2/2)
Signal Name Output Device Serial clock (SCK0) Master Synchronous clock to output address/command/ data, ACK signal, synchronization BUSY signal, etc. Address/ command/data are transferred with the first eight synchronous clocks. Address (A7 to A0) Master 8-bit data to be transferred in synchronization with SCK0 after output of REL and CMD signals
SB0 (SB1) REL CMD SCK0 1 2 7 8
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Definition
Timing Chart
Output Condition
Effects on Flag
Meaning of Signal
When CSIE0 = 1, CSIIF0 set (rising Timing of signal output execution of instruction for edge of 9th clock of SCK0)Note 1 CHAPTER 15 to serial data bus
SCK0
1
2
7
8
9
10
data write to SIO0 (serial transfer
SB0 (SB1)
start instruction)
Note 2
SERIAL INTERFACE CHANNEL 0 (PD78014 Subseries)
Address value of slave device on the serial bus
Address (C7 to C0)
Master
8-bit data to be transferred in synchronization with SCK0 after output of only CMD signal without REL signal output
SB0 (SB1) CMD SCK0 1 2 7 8
Instruction messages to the slave device
Address (D7 to D0)
Master/ slave
8-bit data to be transferred in synchronization with SCK0 without output of REL and CMD signals
SB0 (SB1) CMD SCK0 1 2 7 8
Numeric values to be processed with slave or master device
Notes
1. When WUP = 0, CSIIF0 is always set at the rising edge of the 9th clock of SCK0. When WUP = 1, an address is received. Only when the address matches the slave address register (SVA), CSIIF0 is set (when the address does not match, RELD is cleared). 2. In BUSY state, transfer starts after the READY state is set.
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(5) Pin configuration The serial clock pin SCK0 and serial data bus pin SB0 (SB1) have the following configurations. (a) SCK0 ............ Serial clock input/output pin <1> Master .. CMOS and push-pull output <2> Slave .... Schmitt input (b) SB0 (SB1) .... Serial data input/output dual-function pin Both master and slave devices have an N-ch open-drain output and a Schmitt input. Because the serial data bus line has an N-ch open-drain output, an external pull-up resistor is necessary.
Figure 15-27. Pin Configuration
Slave Device Master Device SCK0 Clock Output Serial Clock (Clock Input) VDD N-ch Open-Drain
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SCK0
(Clock Output) Clock Input
SB0 (SB1)
RL
SB0 (SB1)
N-ch Open-Drain SO0
SO0
Serial Data Bus
SI0
SI0
Caution
Because the N-ch open-drain output must be set to high-impedance at the time of data reception, write FFH to the serial I/O shift register 0 (SIO0) in advance. However, when the wake-up function specification bit (WUP) = 1, the N-ch open-drain output will always be set to high-impedance. Thus, it is not necessary to write FFH to SIO0 before reception.
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(6) Address match detection method In the SBI mode, a particular slave device can be selected by sending a slave address from the master device. Address match detection is automatically executed by hardware. With the slave address register (SVA), and if the wake-up function specification bit (WUP) = 1, CSIIF0 is set only when the selve address transmitted from the master device matches the value set in SVA. If bit 5 (SIC) of the interrupt timing specification register (SINT) is set to 1, the wake-up function dose not operate even with WUP = 1 (an interrupt request signal is generated in detecting a bus release). When the wake-up function is used, clear SIC to 0. Cautions 1. Slave selection/non-selection is detected by matching of the slave address received after bus release (RELD = 1). For this match detection, match interrupt request (INTCSI0) of the address to be generated with WUP = 1 is normally used. Thus, execute selection/non-selection detection by slave address when WUP = 1. 2. When detecting selection/non-selection without the use of interrupt request with WUP = 0, do so by means of transmission/reception of the command preset by program instead of using the address match detection method. (7) Error detection In the SBI mode, the serial bus SB0 (SB1) status being transmitted is fetched into the destination device, that is, the serial I/O shift register 0 (SIO0). Thus, transmit errors can be detected in the following ways: (a) Method of comparing SIO0 data before transmission to that after transmission In this case, if two data differ from each other, a transmit error is judged to have occurred.
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(b) Method of using the slave address register (SVA) Transmit data is set to both SIO0 and SVA and is transmitted. After termination of transmission, the COI bit (match signal coming from the address comparator) of the serial operating mode register 0 (CSIM0) is tested. If it is "1", normal transmission is judged to have been carried out. If it is "0", a transmit error is judged to have occurred.
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(8) Communication operation In the SBI mode, the master device selects normally one slave device as communication target from among two or more devices by outputting an "address" to the serial bus. After the communication target device has been determined, commands and data are transmitted/ received and serial communication is realized between the master and slave devices. Figures 15-28 to 15-31 show data communication timing charts. Shift operation of the serial I/O shift register 0 (SIO0) is carried out at the falling edge of serial clock (SCK0). Transmit data is latched into the SO0 latch and is output with MSB set as the first bit from the SB0/P25 or SB1/ P26 pin. Receive data input to the SB0 (or SB1) pin at the rising edge of SCK0 is latched into the SIO0.
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Figure 15-28. Address Transmission from Master Device to Slave Device (WUP = 1)
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Master Device Processing (Transmitter) Program Processing
Hardware Operation
, , ,
CMDT RELT CMDT Write Set Set Set to SIO0
Interrupt Servicing (Preparation for the Next Serial Transfer)
CHAPTER 15
Serial Transmission
INTCSI0
Generation
ACKD Set
SCK0 Stop
SERIAL INTERFACE CHANNEL 0 (PD78014 Subseries)
Transfer Line
SCK0 Pin
1
2
3
4
5
6
7
8
9
SB0 (SB1) Pin
A7
A6
A5
A4
A3
A2
A1
A0
ACK
BUSY
READY
Address Slave Device Processing (Receiver) Program Processing
WUP0
, , , , , , , ,
ACKT Set BUSY Clear Hardware Operation
CMDD CMDD CMDD Set Clear Set RELD Set
Serial Reception
INTCSI0
ACK BUSY
Generation
Output Output
BUSY Clear
(When SVA = SIO0)
305
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306
Master Device Processing (Transmitter) Program Processing Hardware Operation Transfer Line SCK0 Pin SB0 (SB1) Pin Slave Device Processing (Receiver) Program Processing Hardware Operation
Figure 15-29. Command Transmission from Master Device to Slave Device
,, ,, ,,
CMDT Write Set to SIO0
Interrupt Servicing (Preparation for the Next Serial Transfer) CHAPTER 15
Serial Transmission
INTCSI0
Generation
ACKD Set
SCK0 Stop
SERIAL INTERFACE CHANNEL 0 (PD78014 Subseries)
1
2
3
4
5
6
7
8
9
C7
C6
C5
C4
C3
C2
C1
C0
ACK
BUSY
READY
Command
, , ,, ,, ,, ,, ,,
SIO0 Command ACKT Read analysis Set BUSY Clear
CMDD Set
Serial Reception
INTCSI0
ACK BUSY
Generation
Output Output
BUSY Clear
Figure 15-30. Data Transmission from Master Device to Slave Device
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Master Device Processing (Transmitter) Program Processing
,, ,, ,,
Write to SIO0 Serial Transmission INTCSI0
Generation
Interrupt Servicing (Preparation for the Next Serial Transfer)
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Hardware Operation
ACKD Set
SCK0 Stop
SERIAL INTERFACE CHANNEL 0 (PD78014 Subseries)
Transfer Line SCK0 Pin
1
2
3
4
5
6
7
8
9
SB0 (SB1) Pin
D7
D6
D5
D4 Data
D3
D2
D1
D0
ACK
BUSY
READY
Slave Device Processing (Receiver)
Program Processing
Hardware Operation
,, ,, ,, ,, ,, ,, ,,
SIO0 Read ACKT Set BUSY Clear Serial Reception INTCSI0 ACK BUSY
Generation Output Output
BUSY Clear
307
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308
Master Device Processing (Receiver) Program Processing Hardware Operation Transfer Line SCK0 Pin SB0 (SB1) Pin BUSY Slave Device Processing (Transmitter) Program Processing Hardware Operation
Figure 15-31. Data Transmission from Slave Device to Master Device
,, ,, ,, ,, ,,
FFH Write to SIO0
SIO0 Read
ACKT FFH Write Set to SIO0
Receive Data Processing
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SCK0 Stop
Serial Reception
INTCSI0
Generation
ACK Output
Serial Reception
SERIAL INTERFACE CHANNEL 0 (PD78014 Subseries)
1
2
3
4
5
6
7
8
9
1
2
READY
D7
D6
D5
D4 Data
D3
D2
D1
D0
ACK
BUSY
READY
D7
D6
,, , ,, ,, ,, ,, ,, ,
Write to SIO0 Write to SIO0 BUSY Clear Serial Reception INTCSI0
Generation
ACKD BUSY BUSY Set Output Clear
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SERIAL INTERFACE CHANNEL 0 (PD78014 Subseries)
(9) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. * Serial interface channel 0 operation control bit (CSIE0) = 1 * Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer. Cautions 1. If CSIE0 is set to "1" after data write to SIO0, transfer does not start. 2. Because the N-ch open-drain output must be set to high-impedance at the time of data reception, write FFH to SIO0 in advance. However, when the wake-up function specification bit (WUP) = 1, the N-ch open-drain output will always be set to high-impedance. Thus, it is not necessary to write FFH to SIO0 before reception. 3. If data is written to SIO0 when the slave is busy, the data is not lost. When the busy state is cleared and SB0 (or SB1) input is set to the high level (READY) state, transfer starts. Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0) is set. For pins which are to be used for data input/output, be sure to carry out the following settings before serial transfer of the 1st byte after RESET input. <1> Set the P25 and P26 output latches to 1. <2> Set bit 0 (RELT) of the serial bus interface control register (SBIC) to 1. <3> Reset the P25 and P26 output latches from 1 to 0.
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(10) Distinction method of slave busy state When device is in the master mode, follow the procedure below to judge whether slave device is in the busy state or not. <1> Detect acknowledge signal (ACK) or interrupt request signal generation. <2> Set the port mode register PM25 (or PM26) of the SB0/P25 (or SB1/P26) pin into the input mode. <3> Read out the pin state (when the pin level is high, the READY state is set). After the detection of the READY state, set the port mode register to 0 and return to the output mode. (11) Cautions on SBI mode (a) Slave selection/non-selection is detected by match detection of the slave address received after bus release (RELD = 1). For this match detection, match interrupt request (INTCSI0) of the address to be generated with WUP = 1 is normally used. Thus, execute selection/non-selection detection by slave address when WUP = 1. (b) When detecting selection/non-selection without the use of interrupt with WUP = 0, do so by means of transmission/reception of the command preset by program instead of using the address match detection method.
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(c) In the SBI mode, the BUSY signal is output until the falling of the next serial clock after the BUSY release indication. If WUP = 1 is set by mistake during this period, BUSY will not be released. Thus, after releasing BUSY, be sure to check that the SB0 (SB1) has become high level before setting WUP = 1. (d) For pins which are to be used for data input/output, be sure to carry out the following settings before serial transfer of the 1st byte after RESET input. <1> Set the P25 and P26 output latches to 1. <2> Set bit 0 (RELT) of the serial bus interface control register (SBIC) to 1. <3> Reset the P25 and P26 output latches from 1 to 0. (e) The bus release signal or the command signal is acknowledged when the SCK0 line is in high level, and the SB0 (SB1) line changes from low level to high level or from high level to low level. Thus, if the timing at which bus changes deviates due to effects such as board capacity, it may be determined as the bus release signal (or the command signal) even if data is sent. Therefore perform wiring carefully. 15.4.4 2-wire serial I/O mode operation The 2-wire serial I/O mode can cope with any communication format by program. Communication is basically carried out with two lines of serial clock (SCK0) and serial data input/output (SB0 or SB1).
Figure 15-32. Example of Serial Bus Configuration with 2-Wire Serial I/O
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VDD
VDD
Master
Slave
SCK0
SCK0
SB0 (SB1)
SB0 (SB1)
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(1) Register setting The 2-wire serial I/O mode is set with the serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC) and the interrupt timing specification register (SINT). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H.
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Symbol CSIM0
<7> CSIE0
<6> COI
<5>
4
3
2
1
0
Address FF60H
When Reset 00H
R/W R/WNote 1
WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
R/W
CSIM01 CSIM00 0 1 1 x 0 1
Serial Interface Channel 0 Clock Selection Input clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
R/W
CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27 04 0 1 03 x 0 02
Operating Mode
Start Bit
SI0/SB0/P25 Pin Function
SO0/SB1/P26 Pin Function
SCK0/P27 Pin Function
3-wire serial I/O mode (Refer to 15.4.2 3-wire serial I/O mode operation) SBI mode (Refer to 15.4.3 SBI mode operation)
Note 2 Note 2
2-wire serial 0 0 0 1 I/O mode
MSB
P25 (CMOS input/output)
SB1
SCK0
1
1
0
x
x
(N-ch open-drain (N-ch openinput/output) P26 drain input/output)
Note 2 Note 2
SB0 0 1
1
0
0
x
x
(N-ch open-drain (CMOS input/output) input/output)
R/W
WUP 0 1
Wake-up Function ControlNote 3 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1) matches the slave address register (SVA) data whenthe SBI mode is used
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R
COI 0 1
Slave Address Comparison Result FlagNote 4 Slave address register (SVA) not equal to serial I/O shift register 0 (SIO0) data Slave address register (SVA) equal to serial I/O shift register 0 (SIO0) data
R/W
CSIE0 0 1
Serial Interface Channel 0 Operation Control Operation stopped Operation enable
Notes
1. Bit 6 (COI) is a Read-Only bit. 2. Can be used freely as port function. 3. When 2-wire serial I/O mode is used, be sure to set WUP to 0. 4. When CSIE0 = 0, COI becomes 0.
Remark
x
: don't care
PMxx: Port mode register Pxx : Output latch of port
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(b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H.
Symbol SBIC R/W
<7>
<6>
<5>
<4>
<3>
<2>
<1> CMDT
<0> RELT
Address FF61H
When Reset 00H
R/W R/W
BSYE ACKD ACKE RELT
ACKT CMDD RELD
When RELT = 1, SO latch is set to 1. After SO latch setting, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
R/W
CMDT
When CMDT = 1, SO latch is cleared to 0. After SO latch clearance, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0)
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(c) Interrupt timing specification register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H.
Symbol SINT
7 0
<6> CLD
<5> SIC
<4> SVAM
3 0
2 0
1 0
0 0
Address FF63H
When Reset 00H
R/W R/WNote 1
R/W
SIC 0
INTCSI0 Interrupt Factor Selection CSIIF0 is set (1) upon termination of serial channel 0 transfer
1 R
CSIIF0 is set (1) upon bus release detection
CLD 0 1
SCK0/P27 Pin LevelNote 2 Low Level High Level
Notes
1. Bit 6 (CLD) is a Read-Only bit. 2. When CSIE0 = 0, CLD becomes 0.
Caution Be sure to set bits 0 to 3 to 0.
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Remark
CSIIF0: Interrupt request flag supports the INTCSI0 CSIE0 : Bit 7 of the serial operating mode register 0 (CSIM0)
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(2) Communication operation The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out in synchronization with the falling edge of the serial clock (SCK0). The transmit data is held in the SO0 latch and is output from the SB0/P25 (or SB1/P26) pin with MSB set at start. The receive data input from the SB0 (or SB1) pin is latched into the SIO0 at the rising edge of SCK0. Upon termination of 8-bit transfer, the SIO0 operation stops automatically and the interrupt request flag (CSIIF0) is set.
Figure 15-33. 2-Wire Serial I/O Mode Timings
SCK0
1
2
3
4
5
6
7
8
SB0 (SB1)
D7
D6
D5
D4
D3
D2
D1
D0
CSIIF0 End of Transfer Transfer Start at the falling edge of SCK0
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The SB0 (or SB1) pin specified for the serial data bus serves for N-ch open-drain input/output and thus it must be externally pulled up. Because it is necessary to be set to high-impedance the N-ch open-drain output for data reception, write FFH to SIO0 in advance. The SB0 (or SB1) pin generates the SO0 latch status and thus the SB0 (or SB1) pin output status can be manipulated by setting bit 0 (RELT) or bit 1 (CMDT) of the serial bus interface control register (SBIC). However, do not carry out this manipulation during serial transfer. Control the SCK0 pin output level in the output mode (internal system clock mode) by manipulating the P27 output latch (refer to 15.4.5 SCK0/P27 pin output manipulation).
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(3) Various signals Figure 15-34 shows RELT and CMDT operations.
Figure 15-34. RELT and CMDT Operations
SO0 Latch
RELT
CMDT
(4) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. * Serial interface channel 0 operation control bit (CSIE0)= 1 * Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer. Cautions 1. If CSIE0 is set to "1" after data write to SIO0, transfer does not start. 2. Because the N-ch open-drain output must be set to high-impedance for data reception, write FFH to SIO0 in advance. Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0) is
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(5) Error detection In the 2-wire serial I/O mode, the serial bus SB0 (SBI) status being transmitted is fetched into the destination device, that is, serial I/O shift register 0 (SIO0). Thus, transmit errors can be detected in the following way. (a) Method of comparing SIO0 data before transmission to that after transmission In this case, if two data differ from each other, a transmit error is judged to have occurred. (b) Method of using the slave address register (SVA) Transmit data is set to both SIO0 and SVA and is transmitted. After termination of transmission, the COI bit (match signal coming from the address comparator) of the serial operating mode register 0 (CSIM0) is tested. If it is "1", normal transmission is judged to have been carried out. If it is "0", a transmit error is judged to have occurred. 15.4.5 SCK0/P27 pin output manipulation Because the SCK0/P27 pin incorporates an output latch, static output is also possible by software in addition to normal serial clock output. P27 output latch manipulation enables any value of SCK0 to be set by software (SI0/SB0 and SO0/SB1 pin to be controlled with bit 0 (RELD) or bit 1 (CMDT) of the serial bus interface control register (SBIC)). The SCK0/P27 pin output manipulating procedure is described below. <1> Set the serial operating mode register 0 (CSIM0) (SCK0 pin enabled for serial operation in the output mode). SCK0 = 1 with serial transfer suspended. <2> Manipulate the P27 output latch with a bit manipulation instruction.
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Figure 15-35. SCK0/P27 Pin Configuration
With a bit manipulation instruction SCK0/P27 To Internal Circuit P27 Output Latch
SCK0 (= 1 with a serial transfer suspended) When CSIE0 = 1 and CSIM01 and CSIM00 are 1, 0 or 1, 1 From Serial Clock Control Circuit
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[MEMO]
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78014Y Subseries)
The PD78014Y Subseries incorporates two channels of clock synchronous serial interfaces. Differences between channels 0 and 1 are as follows (Refer to CHAPTER 17 SERIAL INTERFACE CHANNEL 1 for details of the serial interface channel 1) .
Table 16-1. Differences between Channels 0 and 1
Serial Transfer Mode 3-wire serial I/O Clock selection Transfer method Channel 0 Channel 1
fX/22Note, fX/23, fX/24, fX/25, fX/26, fX/27, fX/28, fX/29 external clock, TO2 output clock MSB/LSB switchable as the start bit MSB/LSB switchable as the start bit Automatic transmit/receive function
Transfer end flag SBI (serial bus interface) 2-wire serial I/O I2C bus (Inter IC Bus)
Serial interface channel transfer end interrupt request flag (CSIIF0) Use possible
Serial interface channel transfer end interrupt request flag (CSIIF1 and TRF) None
Note
Can be set only when the main system clock oscillates at 4.19 MHz or less.
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Differences of serial interface channel 0 are shown in Table 16-2.
Table 16-2. Difference of Serial Interface Channel 0 Mode
Operation mode 3-wire serial I/O mode Used pin SCK0, SO0 or SI0 Features * Input and output lines are independent and they can transfer/receive at the same time, so the data transfer processing time is fast. * NEC single-chip microcontrollers provided as before. SBI mode SCK0, SB0 or SB1 * Enables configuration of serial bus with two signal lines, thus, even when connected to some microcontrollers, the number of ports can be cut and wiring and routing on a board can be reduced. * High-speed serial interface compliant with the NEC standard bus format. * Address and command information onto the serial bus 2-wire serial mode SCK0, SB0 or SB1 * Enables configuration of serial bus with two signal lines, thus, even when connected to some microcontrollers, the number of ports can be cut and wiring and routing on a board can be reduced. * Supports any data transfer format by program. I 2C SCL, SDA0 or SDA1
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Usage Serial interface as is the case with the 75X/XL, 78K and 17K series.
* Supports I2C bus format
Application sets using I2C bus (such as TV, VCR, and audio products)
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16.1 Serial Interface Channel 0 Functions Serial interface channel 0 employs the following five modes. * Operation stop mode * 3-wire serial I/O mode * SBI (Serial bus interface) mode * 2-wire serial I/O mode * I2C (Inter IC) bus mode Caution Do not switch the operation mode (3-wire serial I/O/2-wire serial I/O/SBI/I2C bus) during the serial interface channel 0 operation enable. The operation mode should be switched after stopping the serial operation. (1) Operation stop mode Operation stop mode is used when serial transfer is not performed, thus reducing power dissipation. (2) 3-wire serial I/O mode (MSB/LSB-first switchable) 3-wire serial I/O mode transfers 8-bit data with three lines; serial clock (SCK0), serial output (SO0), and serial input (SI0). 3-wire serial I/O mode can transfer/receive at the same time, so the data transfer processing time is fast. The start bit of 8-bit data to undergo serial transfer is switchable between MSB and LSB, so it is possible to connect devices of any start bit. 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate
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a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K and 17K series. (3) SBI (serial bus interface) mode (MSB first) This mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (SCK0) and serial data bus (SB0 or SB1) (see Figure 16-1). The SBI mode complies with the NEC serial bus format and distinguishes the transfer data into "address", "command", and "data" to transmit or receive the data. * Address * Data : Data to select objective devices in serial communication : Data to be actually transferred
* Command : Data to instruct objective devices
In the actual transfer, the master device first outputs the "address" to the serial bus, and selects the slave device as communication target from among two or more devices. The serial transfer is then performed by transmitting and receiving "command" and "data" between the master and slave devices. The receiver automatically distinguishes the received data as "address", "command", or "data", by hardware. This function enables to use input/output ports effectively and to simplify a serial interface controller of application programs. In addition, the wake-up function for handshake, and the acknowledge signal and busy signal output function can be used.
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Figure 16-1. Serial Bus Interface (SBI) System Configuration Example
VDD Master CPU Slave CPU1
SCK0 SB0
SCK0 SB0
Slave CPU2
SCK0 SB0
Slave CPUn
SCK0
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SB0
(4) 2-wire serial I/O mode (MSB-first) This mode is used for 8-bit data transfer using two lines of the serial clock (SCK0) and serial data bus (SB0 or SB1). This mode supports any one of the possible data transfer formats by controlling the SCK0 level and the SB0 or SB1 output level. Thus, the handshake line previously necessary for connecting two or more devices can be removed, resulting in an increased number of available input/output ports.
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Figure 16-2. Serial Bus Configuration Example with 2-Wire Serial I/O
VDD
VDD
Master CPU
Slave
SCK0
SCK0
SB0 (SB1)
SB0 (SB1)
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(5) I2C bus mode (MSB first) This mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (SCL) and serial data bus (SDA0 or SDA1). This mode complies with the NEC I2C bus format. In this mode, the transmitter outputs three kinds of data onto the serial data bus "start condition", "data", and "stop condition". The receiver automatically detects the received data by hardware.
Figure 16-3. Serial Bus Configuration Example Using I2C Bus
VDD VDD Master CPU Slave CPU1
SCL SDA0 (SDA1)
SCL SDA0 (SDA1)
Slave CPU2
SCL SDA0 (SDA1)
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Slave CPUn
SCL SDA0 (SDA1)
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16.2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware.
Table 16-3. Serial Interface Channel 0 Configuration
Item Register Configuration Serial I/O shift register 0 (SIO0) Slave address register (SVA) Control register Timer clock select register 3 (TCL3) Serial operating mode register 0 (CSIM0) Serial bus interface control register (SBIC) Interrupt timing specify register (SINT) Port mode register 2 (PM2)Note
Note
Refer to Figure 6-8 P20, P21, P23 to P26 Block Diagrams (PD78074Y Subseries) and Figure 6-9 P22 and P27 Block diagrams (PD78074Y Subseries).
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Serial Operating Mode Register 0
Control Circuit
Figure 16-4.
Serial Interface Channel 0 Block Diagram
Internal Bus Serial Bus Interface Control Register Slave Address Register (SVA) Match
BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
CSIM CSIE0 COI WUP CSIM CSIM CSIM CSIM 00 04 03 02 01
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SVAM
SDA0/SI0/ SB0/P25 PM25 SDA1/SO0/ SB1/P26
Output Control
Selector
P25 Output Latch
Serial I/O Shift Register 0 (SIO0)
CLR SET
D
Q
SERIAL INTERFACE CHANNEL 0 (PD78014Y Subseries)
PM26
Output Control
Selector P26 Output Latch
Bus Release/ Command/ Acknowledge Detector
ACKD CMDD RELD WUP
Busy/ Acknowledge Output Circuit
CLD SCL/SCK0/P27 PM27
Output Control
Serial Clock Counter Serial Clock Control Circuit CSIM00 CSIM01 P27 Output Latch
Interrupt Request Signal Generator
INTCSI0 TO2 1/16 Divider Selector fX/22 to fX/29
Selector
CSIM00 CSIM01
2
4
CLD SIC SVAM CLC WREL WAT1 WAT0 Interrupt Timing Specification Register Internal Bus
TCL33 TCL32 TCL31 TCL30
Timer Clock Select Register 3
Remark Output Control performs selection between CMOS output and N-ch open-drain output.
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(1) Serial I/O shift register 0 (SIO0) This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO0 is set with an 8-bit memory manipulation instruction. When bit 7 (CSIE0) of serial operating mode register 0 (CSIM0) is 1, writing data to SIO0 starts serial operation. In transmission, data written to SIO0 is output to the serial output (SO0) or serial data bus (SB0/SB1). In reception, data is read from the serial input (SI0) or SB0/SB1 to SIO0. The SBI mode, 2-wire serial I/O mode, and I2C bus mode bus configurations enable the pin to serve for both input and output. Thus, in the case of a device for reception, write FFH to SIO0 in advance (except when address reception is carried out by setting bit 5 (WUP) of CSIM0 to 1). In the SBI mode, the busy state can be cleared by writing data to SIO0. In this case, bit 7 (BSYE) of the serial bus interface control register (SBIC) is not cleared to 0. RESET input makes SIO0 undefined. Caution In the I2C bus mode, do not write data to SIO0 during WUP (bit 5 of serial operation mode register 0 (CSIM0)) = 1. When wake-up function is used, data reception is available without writing data to SIO0. For details about wake-up function, refer to 16.4.5 (1) (c) "Wake-up function". (2) Slave address register (SVA) This is an 8-bit register to set the slave address value for connection of a slave device to the serial bus. SVA is set with an 8-bit memory manipulation instruction. This register does not be used in the 3-wire serial I/O mode. The master device outputs a slave address for selection of a particular slave device to the connected slave device. These two data (the slave address output from the master device and the SVA value) are compared with an
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address comparator. If they match, the slave device has been selected. In that case, bit 6 (COI) of serial operating mode register 0 (CSIM0) becomes 1. Address comparison can also be executed on the data of LSB-masked high-order 7 bits when bit 4 (SVAM) of the interrupt timing specification register (SINT) is 1. If no matching is detected in address reception, bit 2 (RELD) of the serial bus interface control register (SBIC) is cleared to 0. In the SBI mode or the I2C bus mode, when bit 5 (WUP) of CSIM0 is 1, the wake-up function can be used. In this case, the interrupt request signal (INTCSI0) is generated only if the slave address output from the master device matches the SVA value. With this interrupt request, the slave device acknowledges that a communication request is sent from the master device. When bit 5 (SIC) of the interrupt timing specification register (SINT) has been set to 1, the wake-up function is not available even if WUP IS 1. (The interrupt request signal is generated at the bus release in the SBI mode, and at the stop condition in the I2C mode. The SIC must be cleared to 0 while in use of the wake-up function. Further, when SVA transmits data as the master or slave device in the SBI mode, 2-wire serial I/O mode, or I2C bus mode, SVA can be used to detect errors. RESET input makes SVA undefined.
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(3) SO0 latch This latch holds SI0/SB0/SDA0/P25 and SO0/SB1/SDA1/P26 pin levels. It can be directly controlled by software. In the SBI mode, this latch is set upon termination of the 8th serial clock. (4) Serial clock counter This counter counts the serial clocks to be output and input during transmission/reception and to check whether 8-bit data has been transmitted/received. (5) Serial clock control circuit This circuit controls serial clock supply to the serial I/O shift register 0 (SIO0). When the internal system clock is used, the circuit also controls clock output to the SCK0/SCL/P27 pin. (6) Interrupt request signal generator This circuit controls interrupt request signal generation. It generates the interrupt request signal by setting bits 0, 1 (WAT0, WAT1) of the interrupt timing specify register (SINT) and bit 5 (WUP) of the serial operation mode register 0 (CSIM0) as shown in Table 16-4. (7) Busy/acknowledge output circuit and bus release/command/acknowledge detector These two circuits output and detect various control signals when the SBI mode or I2C bus mode is used. These do not operate in the 3-wire serial I/O mode and 2-wire serial I/O mode.
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Table 16-4. Serial Interface Channel 0 Interrupt Request Signal Generation
Serial Transfer Mode 3-wire or 2-wire serial I/O mode WUP 0 WAT1 WAT0 ACKE 0 0 0 Description An interrupt request signal is generated each time 8 serial clocks are counted. Other than above SBI mode 0 0 0 0/1 Setting prohibited An interrupt request signal is generated each time 8 serial clocks are counted (8-clock wait). 1 After address is received, if the values of the serial I/O shift register 0 (SIO0) and the slave address register (SVA) match, an interrupt request signal is generated. Other than above I C bus mode (transmit)
2
Setting prohibited 0 0 An interrupt request signal is generated each time 8 serial clocks are counted (8-clock wait). Normally, during transmission the settings WAT1, WAT0 = 1, 0, are not used. They are used only when wanting to coordinate receive time and processing systematically using software. ACK information is generated by the receiving side, thus ACKE should be set to 0 (disable).
0
1
1
1
0
An interrupt request signal is generated each time 9 serial clocks are counted (9-clock wait). ACK information is generated by the receiving side, thus ACKE should be set to 0 (disable).
Other than above
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Setting prohibited 0 0 An interrupt request signal is generated each time 8 serial clocks are counted (8-clock wait). ACK information is output by manipulating ACKT by software after an interrupt is generated.
I C bus mode (receive)
2
0
1
1
1
0/1
An interrupt request signal is generated each time 9 serial clocks are counted (9-clock wait). To automati cally generate ACK information, preset ACKE to 1 (enable) before transfer start. However, in the case of the master, set ACKE to 0 (disable) before receiving the last data.
1
1
1
1
After address is received, if the values of the serial I/O shift register 0 (SIO0) and the slave address register (SVA) match, an interrupt request signal is generated. To automatically generate ACK information, preset ACKE to 1 (enable) before transfer start.
Other than above
Setting prohibited
Remark ACKE: Bit 5 of serial bus interface control register (SBIC)
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16.3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0. * Timer clock select register 3 (TCL3) * Serial operating mode register 0 (CSIM0) * Serial bus interface control register (SBIC) * Interrupt timing specification register (SINT) (1) Timer clock select register 3 (TCL3) (See Figure 16-5) This register sets the serial clock of serial interface channel 0. TCL3 is set with an 8-bit memory manipulation instruction. RESET input sets TCL3 to 88H. Remark TCL3 has functions to set the serial clock of serial interface channel 1 except to set the serial clock of serial interface channel 0. (2) Serial operating mode register 0 (CSIM0) (See Figure 16-6) This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop, wake-up function and displays the address comparator match signal. CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H. Caution
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Do not switch the operation mode (3-wire serial I/O/2-wire serial I/O/SBI I2C bus) during the serial interface channel 0 operation enable. The operation mode should be switched after stopping the serial operation.
(3) Serial bus interface control register (SBIC) (See Figure 16-7) This register sets the serial bus interface operation and displays the status. SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. (4) Interrupt timing specify register (SINT) (See Figure 16-8) This register sets interrupt, wait, clock level control, address mask function and displays the level status of SCK0/ SCL/P27 pin. SINT is set with 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H.
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Figure 16-5. Timer Clock Select Register 3 Format
Symbol TCL3 7 6 5 4 3 2 1 0 Address FF43H When Reset 88H R/W R/W
TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 TCL33 TCL32 TCL31 TCL30
Serial Interface Channel 0 Serial Clock Seletion Serial Clock in I2C bus mode Serial Clock in 3-wire/SBI/2-wire mode fX/22
Note
0 0 1 1 1 1 1 1
1 1 0 0 0 0 1 1
1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1
fX/2 (156 kHz) fX/27 (78.1 kHz) fX/2 (39.1 kHz) fX/29 (19.5 kHz) fX/2
10 8
6
fX/23 (1.25 MHz) fX/24 (625 kHz) fX/25 (313 kHz) fX/26 (156 kHz) fX/27 (78.1 kHz) fX/28 (39.1 kHz) fX/29 (19.5 kHz)
(9.8 kHz)
fX/211 (4.9 kHz) fX/2
12
(2.4 kHz)
fX/213 (1.2 kHz) Setting prohibited
Other than above TCL37 TCL36 TCL35 TCL34 0 0 1 1 1 1
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Serial Interface Channel 1 Serial Clock Seletion fX/22
Note
1 1 0 0 0 0 1 1
1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1
fX/23 (1.25 MHz) fX/24 (625 kHz) fX/25 (313 kHz) fX/26 (156 kHz) fX/27 (78.1 kHz) fX/28 (39.1 kHz) fX/29 (19.5 kHz) Setting prohibited
1 1
Other than above
Note
Can be set only when the main system clock oscillate at 4.19 MHz or less. If TCL3 is to be rewritten in data other than identical data, the serial transfer must be stopped first. 1. 2. fX: Main system clock oscillation frequency Value in parentheses apply to operation with fX = 10.0 MHz.
Caution Remarks
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Figure 16-6. Serial Operating Mode Register 0 Format (1/2)
Symbol CSIM0 R/W <7> CSIE0 <6> COI <5> 4 3 2 1 0 Address FF60H When Reset 00H R/W R/WNote 1
WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection 0 1 1 x 0 1 Input clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) outputNote 2 Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
R/W
CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27
Operating Mode
Start Bit
SI0/SB0/SDA0/ SO0/SBI/SDA1/
SCK0/SCL/P27
04 0
03 x
02 0 1 1 x 0 0 0 1
P25 Pin Function P26 Pin Function Pin Function MSB LSB SI0Note 3 (Input) SO0 (CMOS output) MSB P25 (CMOS input/output) SB1 SCK0 (CMOS input/output) SCK0
3-wire serial I/O mode
Note 4 Note 4
SBI mode 0 0 0 1
1
0
0
x
x
(N-ch open-drain (CMOS input/output) P26 input/output)
Note 4 Note 4
SB0 0 1
1
0
0
x
x
(N-ch open-drain (CMOS input/ input/output) output) SB1/SDA1 SCK0/SCL
Note 4 Note 4
2-wire serial MSB 0 0 0 1 I/O mode or I2C Bus
P25 (CMOS input/output) SB0/SDA0
1
1
0
x
x
(N-ch open-drain (N-ch openinput/output) P26 drain input/ output)
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Note 4 Note 4
Mode 0 1
1
0
0
x
x
(N-ch open-drain (CMOS input/output) input/output)
R/W
WUP Wake-up Function ControlNote 5 0 1 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1 in the SBI mode, CMDD = 1 in the I2C bus mode) matches the slave address register (SVA) data when SBI mode or I2C bus mode is used.
Notes
1. Bit 6 (COI) is a Read-Only bit. 2. When the I2C mode is used, the clock gets to 1/16 clock frequency which TO2 outputs. 3. Can be used as P25 (CMOS input) when used only for transmission. 4. Can be used freely as port function. 5. When the wake-up function is used (WUP = 1), set bit 5 of the interrupt timing specification register (SINT) to 0. Do not write data to serial I/O shift register 0 (SIO0) during WUP = 1.
Remark
x
: Don't care
PMxx: Port mode register Pxx : Output latch of port
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Figure 16-6. Serial Operating Mode Register 0 Format (2/2)
R
COI 0 1
Slave Address Comparison Result FlagNote Slave address register (SVA) not equal to serial I/O shift register 0 (SIO0) data Slave address register (SVA) equal to serial I/O shift register 0 (SIO0) data Serial Interface Channel 0 Operation Control Operation stopped Operation enabled
R/W
CSIE0 0 1
Note
When CSIE0 = 0, COI becomes 0.
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Figure 16-7. Serial Bus Interface Control Register Format (1/2)
Symbol SBIC <7> <6> <5> <4> <3> <2> <1> CMDT <0> RELT Address FF61H When Reset 00H R/W R/WNote
BSYE ACKD ACKE
ACKT CMDD RELD
R/W
RELT
Use for bus release signal output when the SBI mode is used. Use for stop condition output when the I2C bus mode is used. When RELT = 1, SO latch is set to 1. After SO latch setting, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
R/W
CMDT
Use for command signal output when the SBI mode is used. Use for start condition output in the I2C bus mode. When CMDT = 1, SO latch is cleared to (0). After SO latch clearance, automatically cleared to (0). Also cleared to (0) when CSIE0 = 0.
R
RELD
Bus Release Detection Set Conditions (RELD = 1) * When bus release signal (REL) is detected in the SBI mode * When stop condition is detected in the I2C bus mode
Clear Conditions (RELD = 0) * When transfer start instruction is executed * If SIO0 and SVA values do not match in address reception * When CSIE0 = 0 * When RESET input is applied R
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CMDD
Command Detection Set Conditions (CMDD = 1) * When command signal (CMD) is detected in the SBI mode * When stop condition is detected in the I2C mode
Clear Conditions (CMDD = 0) * When transfer start instruction is executed * When bus release signal (REL) is detected * When stop condition is detected in the I2C bus mode * When CSIE0 = 0 * When RESET input is applied
R/W
ACKT
When the SBI mode is used, acknowledge signal is output in synchronization with the falling edge of SCK0 clock immediately after execution of the instruction to be set to 1, and after acknowledge signal output, automatically cleared to 0. Used as ACKE = 0. Also cleared to 0 upon start of serial interface transfer or when CSIE0 = 0. When the I2C bus mode is used, SDA0 (SDA1) is made low-level until the next SCL falling edge immediately after executionof the set instruction (ACKT = 1). Used to generate ACK signal by software when 8-clock wait is selected. Cleared to (0) upon start of serial interface transfer or when CSIE = 0.
Note
Bits 2, 3, and 6 (RELD, CMDD and ACKD) are read-only bits. 1. 2. Zeros will be returned form bits 0, 1, and 4 (or RELT, CMDT, ACKT, respectively) if users read these bits after data setting is completed. CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0)
Remarks
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Figure 16-7. Serial Bus Interface Control Register Format (2/2)
R/W ACKE 0 1 Acknowledge Signal Automatic Output Control (in SBI mode) Acknowledge signal automatic output disable (output with ACKT enable) Before completion of transfer After completion of transfer Acknowledge signal is output in synchronization with the 9th clock falling edge of SCK0 (automatically output when ACKE = 1). Acknowledge signal is output in synchronization with the falling edge of SCK0 clock immediately after execution of the instruction to be set to 1 (automatically output when ACKE = 1). However, not automatically cleared to 0 after acknowledge signal output. R/W ACKE 0 Acknowledge Signal Automatic Output ControlNote 1 (in the I2C bus mode) Disables acknowledge signal automatic output. (However, output with ACKT possible) Use for reception when 8-clock wait mode is selected or for transmissionNote 2. 1 Enables acknowledge signal automatic output. Outputs acknowledge signal in synchronization with the 9th clock falling edge of SCL (automatically output when ACKE = 1). However, not automatically cleared to 0 after acknowledge signal output. Used in reception with 9-clock wait mode selected.
R
ACKD
Acknowledge Detection Set Conditions (ACKD = 1) * When acknowledge signal is detected at the rising edge of SCK0/SCL clock after completion of transfer
Clear Conditions (ACKD = 0) * At the falling edge of SCK0 clock immediately after the busy mode has been released when a transfer start instruction is executed * Upon execution of transfer start instruction in the I2C
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bus mode * When CSIE0 = 0 * When RESET input is applied
R/W
Note 3
Synchronizing Busy Signal Output Control
BSYE 0 When the SBI mode is used, disables busy signal which is output in synchronization with the falling edge of SCK0 clock immediately after execution of the instruction to be cleared to 0. Be sure to set BSYE
to 0 in the I2C bus mode.
1 Outputs busy signal at the falling edge of SCK0 clock following the acknowledge signal when the SBI mode is used.
Notes
1. Setting should be performed before transfer. 2. If 8-clock wait mode is selected, the acknowledge signal at reception time must be output using ACKT. 3. The busy mode can be cancelled by start of serial interface. However, the BSYE flag is not cleared to 0.
Remark CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0)
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Figure 16-8. Interrupt Timing Specification Register Format (1/2)
Symbol SINT 7 0 <6> CLD <5> SIC <4> SVAM <3> CLC <2> 1 0 WAT0 Address FF63H When Reset 00H R/W R/WNote 1
WREL WAT1
R/W
WAT1 WAT0 0 0
Wait and Interrupt Control Generates interrupt service request at rising edge of 8th SCK0 clock cycle. (Keeping clock output in high impedance)
0 1
1 0
Setting prohibited Used in I2C bus mode (8-clock wait) Generates interrupt service request at rising edge of 8th SCL clock cycle. (In the case of master device, makes SCL output low to enter wait state after output. In the case of slave device, makes SCL output low to request wait pulses are input.)
1
1
Used in I2C bus mode. (9-clock wait) Generates interrupt service request at rising edge of 9th SCL clock cycle. (In the case of master device, makes SCL output low to enter wait state after output. In the case of slave device, makes SCL output low to request waits pulses are input.)
R/W
WREL 0 1
Wait State Cancellation Control Wait state has been cancelled. Cancels wait state. Automatically cleared to 0 when the state is cancelled. (Used to cancel wait state by means of WAT0 and WAT1.)
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R/W
CLC 0
Clock Level ControlNote 2 Used in I2C bus mode. Make output level of SCL pin low unless serial transfer is being performed.
1
Used in I2C bus mode. Make SCL pin enter high-impedance state unless serial transfer is being performed (except for clock line which is kept high) Use to enable master device to generate start condition and stop condition signal.
Notes
1. Bit 6 (CLD) is a Read-Only bit. 2. When not using the I2C bus mode, set CLC to 0.
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Figure 16-8. Interrupt Timing Specification Register Format (2/2)
R/W SVAM 0 1 SVA Bit to be Used as Slave Address Bits 0 to 7 Bits 1 to 7
R/W
SIC 0 1
INTCSI0 Interrupt Cause SelectionNote 1 CSIIF0 is set to 1 upon termination of serial interface channel 0 transfer CSIIF0 is set to 1 upon stop condition detection in the I2C bus mode or termination of serial interface in the SBI mode
R
CLD 0 1
SCK0/SCL/P27 Pin LevelNote 2 Low level High level
Notes
1. When using wake-up function, set SIC to 0. 2. When CSIE0 = 0, CLD becomes 0.
Remark
SVA
: Slave address register
CSIIF0 : Interrupt request flag supports the INTCSI0 CSIE0 : Bit 7 of the serial operating mode register 0 (CSIM0)
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16.4 Serial Interface Channel 0 Operations The following four operating modes are available to the serial interface channel 0. * Operation stop mode * 3-wire serial I/O mode * SBI mode * 2-wire serial I/O mode * I2C (Inter IC) bus mode 16.4.1 Operation stop mode Serial transfer is not carried out in the operation stop mode. Thus, power dissipation can be reduced. The serial I/O shift register 0 (SIO0) does not carry out shift operation either and thus it can be used as normal 8-bit register. In the operation stop mode, the P25/SI0/SB0/SDA0, P26/SO0/SB1/SDA1 and P27/SCK0/SCL pins can be used as normal input/output ports. (1) Register setting The operation stop mode is set with the serial operating mode register 0 (CSIM0). CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H.
Symbol CSIM0
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<7> CSIE0
<6> COI
<5>
4
3
2
1
0
Address FF60H
When Reset 00H
R/W R/W
WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
R/W
CSIE0 0 1
Serial Interface Channel 0 Operation Control Operation stopped Operation enable
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16.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K series. Communication is carried out with three lines of serial clock (SCK0), serial output (SO0), and serial input (SI0). (1) Register setting The 3-wire serial I/O mode is set with the serial operating mode register 0 (CSIM0) and serial bus interface control register (SBIC). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H.
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Symbol CSIM0
<7> CSIE0
<6> COI
<5>
4
3
2
1
0
Address FF60H
When Reset 00H
R/W R/WNote 1
WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
R/W
CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection 0 1 1 x 0 1 Input clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
R/W
CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27
Operating Mode
Start Bit
SI0/SB0/SDA0/ P25 Pin Function
SO0/SB1/SDA1/ P26 Pin Function
SCK0/SCL/ P27 Pin Function
04 0
03 x
02 0 1 1 x 0 0 0 1
3-wire serial I/O mode
MSB LSB
SI0
Note 2
SO0 (CMOS output)
SCK0 (CMOS input/output)
(Input)
1 1
0 1
SBI mode (Refer to 16.4.3 SBI mode operation) 2-wire serial I/O mode (Refer to 16.4.4 2-wire serial I/O mode operation) or I2C bus mode (Refer to 16.4.5 I2C bus mode operation)
R/W
WUP 0 1
Wake-up Function ControlNote 3 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1 in the SBI mode or CMDD = 1 in the I2C bus mode) matches the slave address register data (SVA) when the SBI or I2C bus mode is used.
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R/W
CSIE0 0 1
Serial Interface Channel 0 Operation Control Operation stopped Operation enable
Notes
1. Bit 6 (COI) is a Read-Only bit. 2. Can be used as P25 (CMOS input) when used only for transmission. 3. Be sure to set WUP to 0 when the 3-wire serial I/O mode is selected.
Remark
x
: don't care
PMxx: Port mode register Pxx : Output latch of port
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(b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H.
Symbol SBIC <7> <6> <5> <4> <3> <2> <1> CMDT <0> RELT Address FF61H When Reset 00H R/W R/W
BSYE ACKD ACKE
ACKT CMDD RELD
R/W
RELT
When RELT = 1, SO latch is set to 1. After SO latch setting, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
R/W
CMDT
When CMDT = 1, SO latch is cleared to 0. After SO latch clearance, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0)
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(2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization of the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out at the falling edge of the serial clock (SCK0). The transmitted data is held in the SO0 latch and is output from the SO0 pin. The received data input to the SI0 pin is latched in SIO0 at the rising edge of SCK0. Upon termination of 8-bit transfer, SIO0 operation stops automatically and the interrupt request flag (CSIIF0) is set.
Figure 16-9. 3-Wire Serial I/O Mode Timings
SCK0
1
2
3
4
5
6
7
8
SI0
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
CSIIF0
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Transfer Start at the falling edge of SCK0
End of Transfer
The SO0 pin serves for CMOS output and generates the SO0 latch status. Thus, the SO0 pin output status can be manipulated by setting bit 0 (RELT) and bit 1 (CMDT) of the serial bus interface control register (SBIC). However, do not carry out this manipulation during serial transfer. Control the SCK0 pin output level in the output mode (internal system clock mode) by manipulating the P27 output latch (refer to 16.4.8 SCK0/SCL/P27 pin output manipulation).
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(3) Various signals Figure 16-10 shows RELT and CMDT operations.
Figure 16-10. RELT and CMDT Operations
SO0 Latch
RELT
CMDT
(4) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start at MSB or LSB. Figure 16-11 shows the configuration of the serial I/O shift register 0 (SIO0) and internal bus. As shown in the figure, MSB/LSB can be read/written in inverted form. MSB/LSB switching as the start bit can be specified with bit 2 (CSIM02) of the serial operating mode register 0 (CSIM0).
Figure 16-11. Circuit of Switching in Transfer Bit Order
7 6
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Internal Bus 1 0 LSB Start MSB Start Read/Write Gate Read/Write Gate
SO0 Latch SI0 Shift Register 0 (SIO0) D Q
SO0
SCK0
Start bit switching is realized by switching the bit order for data write to SIO0. The SIO0 shift order remains unchanged. Thus, switch the MSB/LSB start bit before writing data to the shift register.
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(5) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. * Serial interface 0 operation control bit (CSIE0) = 1 * Internal serial clock is stopped or SCK0 is the high level after 8-bit serial transfer. Caution If CSIE0 is set to "1" after data write to SIO0, transfer does not start. Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0) is set. 16.4.3 SBI mode operation SBI (Serial Bus Interface) is a high-speed serial interface in compliance with the NEC serial bus format. SBI has a format with the bus configuration function added to the clocked serial I/O method so that it can carry out communication with two or more devices with two signal conductors on the single-master high-speed serial bus. Thus, when making up a serial bus with two or more microcomputers and peripheral ICs, the number of ports to be used and the number of wires on the board can be decreased. The master device can output to the serial data bus of the slave device "addresses" for selection of the serial communication target device, "commands" to instruct the target device and actual "data". The slave device can identify the received data into "address", "command" or "data", by hardware. This function enables the application program to control serial interface channel 0 to be simplified. The SBI function is incorporated into various devices including 75X/XL Series devices and 78K Series. Figure 16-12 shows a serial bus configuration example when a CPU having a serial interface compliant with SBI
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and peripheral ICs are used. In SBI, the SB0 (SB1) serial data bus pin serves for open-drain output and so the serial data bus line is in wiredOR state. A pull-up resistor is necessary for the serial data bus line. Refer to (11) Cautions on SBI mode (d) described later when the SBI mode is used.
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Figure 16-12. Example of Serial Bus Configuration with SBI
VDD
SCK0 Master CPU SB0 (SB1)
Serial Clock Serial Data Bus
SCK0 SB0 (SB1)
Slave CPU Address 1
SCK0 SB0 (SB1)
Slave CPU Address 2
SCK0 SB0 (SB1)
Slave IC Address N
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Caution
When replacing the master CPU/slave CPU, a pull-up resistor is necessary for the serial clock line (SCK0) as well because serial clock line (SCK0) input/output switching is carried out asynchronously between the master and slave CPUs.
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(1) SBI functions In the conventional serial I/O method, when a serial bus is constructed by connecting two or more devices, many ports and wiring are necessary to distinguish chip select signals and command/data and to judge the busy state because only the data transfer function is available. If these operations are to be controlled by software, the software must be heavily loaded. In SBI, a serial bus can be constructed with two signal conductors of serial clock SCK0 and serial data bus SB0 (SB1). Thus, SBI is effective to decrease the number of microcontroller ports and that of wiring and routing on the board. The SBI functions are described below. (a) Address/command/data identify function Serial data is distinguished into addresses, commands and data. (b) Chip select function by address transmission The master executes slave chip selection by address transmission. (c) Wake-up function The slave can easily judge address reception (chip select judgment) with the wake-up function (which can be set/reset by software). When the wake-up function is set, the interrupt request signal (INTCSI0) is generated upon reception of a match address. Thus, when communication is executed with two or more devices, the CPU except the selected slave devices can operate regardless of serial communication.
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(d) Acknowledge signal (ACK) control function The acknowledge signal to check serial data reception is controlled. (e) Busy signal (BUSY) control function The busy signal to report the slave busy state is controlled.
(2) SBI definition The SBI serial data format is defined as follows. Serial data to be transferred with SBI is distinguished into three types, "address", "command" and "data". Figure 16-13 shows the address, command and data transfer timings.
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Figure 16-13. SBI Transfer Timings
Address Transfer
SCK0
8
9
SB0 (SB1) Bus Release Signal
A7 Address Command Signal
A0
ACK
BUSY
Command Transfer
SCK0
9
SB0 (SB1)
C7 Command
C0 ACK
BUSY
READY
Data Transfer
SCK0
8
9
SB0 (SB1)
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D7 Data
D0 ACK
BUSY
READY
Remark The broken line indicates the READY state. The bus release signal and the command signal are output by the master device. BUSY is output by the slave signal. ACK can be output by either the master or slave device (normally, the 8-bit data receiver outputs). Serial clocks continue to be output by the master device from 8-bit data transfer start to BUSY reset.
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(a) Bus release signal (REL) The bus release signal is generated when the SCK0 line is in high level (a serial clock is not output) and the SB0 (SB1) line changes from low level to high level. The bus release signal is output by the master.
Figure 16-14. Bus Release Signal
SCK0
"H"
SB0 (SB1)
The bus release signal indicates the master will send the address to the slave. The slave contains hardware to detect the bus release signal. Caution The bus release signal is acknowledged when the SCK0 line is in high level, and the SB0 (SB1) line changes from low level to high level. Thus, if the timing at which bus changes deviates due to effects such as board capacity, it may be determined as the bus release signal even if data is sent. Therefore perform wiring carefully. (b) Command Signal (CMD) The command signal is generated when the SCK0 line is in high level (a serial clock is not output) and the
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SB0 (SB1) line changes from high level to low level. The command signal is output by the master.
Figure 16-15. Command Signal
SCK0 SB0 (SB1)
"H"
The command signal indicates that master will send the command to the slave (However, the command signal following the bus release signal indicates that address will be sent). The slave contains hardware to detect the command signal. Caution The command signal is acknowledged when the SCK0 line is in high level, and the SB0 (SB1) line changes from high level to low level. Thus, if the timing at which bus changes deviates due to effects such as board capacity, it may be determined as the command signal even if data is sent. Therefore perform wiring carefully.
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(c) Address The address is 8-bit data that the master outputs to the slave connected to the bus line to select a specific slave.
Figure 16-16. Address
SCK0 SB0 (SB1) 1 A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 A0
Address Bus Release Signal Command Signal
8-bit data following the bus release signal and the command signal is defined as the address. The slave detects the condition and checks by hardware if 8-bit data matches its specified number (the slave address). When 8-bit data matches the slave address, which means the slave is selected, the slave communicates with the master until the master instructs disconnection.
Figure 16-17. Slave Selection with Address
Master Slave 2 Address Transmission
Slave 1
Non-Selection
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Slave 2
Selection
Slave 3
Non-Selection
Slave 4
Non-Selection
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(d) Command and Data The master sends commands and sends/receives data to the slave selected by sending the address.
Figure 16-18. Command
SCK0 SB0 (SB1)
1 C7
2 C6
3 C5
4 C4
5 C3
6 C2
7 C1
8 C0
Command Signal
Command
Figure 16-19. Data
SCK0 SB0 (SB1)
1 D7
2 D6
3 D5
4 D4
5 D3
6 D2
7 D1
8 D0
Data
8-bit data following the command signal is defined as a command. 8-bit data without the command signal is defined as data. How to use the command and data can be determined depending on the communication specifications.
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(e) Acknowledge signal (ACK) This signal is used between the sending side and receiving side devices for confirmation of correct serial data sending.
Figure 16-20. Acknowledge Signal [When output synchronously with SCK0 in 11th clock]
8 9 10 11
SCK0
SB0 (SB1)
ACK
[When output synchronously with SCK0 in 9th clock]
SCK0 8 9
SB0 (SB1)
ACK
Remark
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The broken line indicates the READY state.
The acknowledge signal is a one-shot pulse synchronous with SCK0 falling, whose position can be synchronized with SCK0 in any clock. The sending side that has transferred 8-bit data checks if the acknowledge signal has been sent from the receiving side. If this signal is not sent back from the slave device for a given period after data sending, this means that the data sent has not been received correctly by the slave device.
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(f)
Busy signal (BUSY), Ready signal (READY) The busy signal informs the master that the slave is busy transmitting/receiving data. The ready signal informs the master that the slave is ready to transmit/receive data.
Figure 16-21. Busy Signal, Ready Signal
SCK0 8 9
SB0 (SB1)
ACK
BUSY
READY
Remark
The broken line indicates the ready state.
In the SBI mode, the slave informs the master of the busy state by setting SB0 (SB1) line to low level. The busy signal is output following the acknowledge signal the slave outputs. The busy signal is set/cleared synchronously with the falling edge of SCK0. The master terminates automatically to output the serial clock SCK0 when the busy signal is cleared. The master can start subsequent transmissions when the busy signal is cleared and changes to the ready state. Caution In the SBI mode, the BUSY signal is output until the falling of the next serial clock after the BUSY release indication. If WUP = 1 is set by mistake during this period, BUSY will not be released. Thus, after releasing BUSY, be sure to check that the SB0 (SB1) has
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become high level before setting WUP = 1.
(3) Register setting The SBI mode is set with the serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC), and the interrupt timing specification register (SINT). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H.
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Symbol CSIM0 R/W
<7> CSIE0
<6> COI
<5>
4
3
2
1
0
Address FF60H
When Reset 00H
R/W R/WNote 1
WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection 0 1 1 x 0 1 Input clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock selection register 3 (TCL3)
R/W
CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27
Operating Mode
Start Bit
SI0/SB0/SDA0/ P25 Pin Function
SO0/SB0/SDA1/ P26 Pin Function
SCK0/SCL/P27 Pin Function
04 0
03 x 0
02
3-wire serial I/O mode (Refer to 16.4.2 3-wire serial I/O mode operation)
Note 2 Note 2
SBI mode 0 0 0 1
MSB
P25 (CMOS input/output)
SB1
SCK0
1
0
x
x
(N-ch open-drain (CMOS input/output) P26 input/output)
Note 2 Note 2
SB0 0 1
1
0
0
x
x
(N-ch open-drain (CMOS input/ input/output) output)
1
1
2-wire serial I/O mode (Refer to 16.4.4 2-wire serial I/O mode operation) or I2C bus mode (Refer to 16.4.5 I2C bus mode operation)
R/W
WUP 0 1
Wake-up Function ControlNote 3 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1) matches the slave address register (SVA) data when SBI mode is used
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R
COI 0 1
Slave Address Comparison Result FlagNote 4 Slave address register (SVA) not equal to serial I/O shift register 0 (SIO0) data Slave address register (SVA) equal to serial I/O shift register 0 (SIO0) data
R/W
CSIE0 0 1
Serial Interface Channel 0 Operation Control Operation stopped Operation enable
Notes
1. Bit 6 (COI) is a Read-Only bit. 2. Can be used freely as port function. 3. When the wake-up function is used, set bit 5 of the interrupt timing specification register (SINT) to 0. Do not write data to serial I/O shift register 0 (SIO0) during WUP = 1. 4. When CSIE0 = 0, COI becomes 0.
Remark
x
: don't care
PMxx: Port mode register Pxx : Output latch of port
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(b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H.
Symbol SBIC R/W <7> <6> <5> <4> <3> <2> <1> CMDT <0> RELT Address FF61H When Reset 00H R/W R/WNote
BSYE ACKD ACKE RELT
ACKT CMDD RELD
Use for bus release signal output when the SBI mode is used. When RELT = 1, SO latch is set to 1. After SO latch setting, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
R/W
CMDT
Use for command signal output when the SBI mode is used. When CMDT = 1, SO latch is cleared to 0. After SO latch clearance, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
R
RELD
Bus Release Detection Set Conditions (RELD = 1) * When bus release signal (REL) is detected in the SBI mode
Clear Conditions (RELD = 0) * When transfer start instruction is executed * If SIO0 and SVA values do not match in address reception (only if WUP = 1) * When CSIE0 = 0 * When RESET input is applied
R
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CMDD
Command Detection Set Conditions (CMDD = 1) * When command signal (CMD) is detected in the SBI mode
Clear Conditions (CMDD = 0) * When transfer start instruction is executed * When bus release signal (REL) is detected in the SBI mode * When CSIE0 = 0 * When RESET input is applied
R/W
ACKT
When the SBI mode is used, acknowledge signal is output in synchronization with the falling edge of SCK0 clock immediately after execution of the instruction to be set to 1, and after acknowledge signal output, automatically cleared to 0. Used as ACKE = 0. Also cleared to 0 upon start of serial interface transfer or when CSIE0 = 0. (continued)
Note
Bits 2, 3 and 6 (RELD, CMDD, and ACKD) are Read-Only bits. 1. 2. Zeros will be returned form bits 0, 1, and 4 (or RELT, CMDT, ACKT, respectively) if users read these bits after data setting is completed. CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0)
Remarks
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(continued) R/W ACKE 0 1 Acknowledge Signal Automatic Output Control (in the SBI mode) Acknowledge signal automatic output disable (output with ACKT enable) Before completion of transfer After completion of transfer Acknowledge signal is output in synchronization with the 9th clock falling edge of SCK0 (automatically output when ACKE = 1). Acknowledge signal is output in synchronization with the falling edge of SCK0 clock immediately after execution of the instruction to be set to 1 (automatically output when ACKE = 1). However, not automatically cleared to 0 after acknowl edge signal output.
R
ACKD
Acknowledge Detection Set Conditions (ACKD = 1) * When acknowledge signal (ACK) is detected at the rising edge of SCK0 clock after completion of transfer
Clear Conditions (ACKD = 0) * In the SBI mode, at the falling edge of SCK0 clock immediately after the busy mode has been released when a transfer start instruction is executed * When CSIE0 = 0 * When RESET input is applied
R/W
BSYENote
Synchronizing Busy Signal Output Control When the SBI mode is used, disables busy signal which is output in synchronization with the falling edge of SCK0 clock immediately after execution of the instruction to be cleared to 0 (with READY state).
0
1
When the SBI mode is used, outputs busy signal at the falling edge of SCK0 clock following the acknowledge signal.
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Note
The busy mode can be cleared by start of serial interface transfer. However, the BSYE flag is not cleared to 0.
Remark CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0)
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(c) Interrupt timing specification register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H.
Symbol SINT
7 0
<6> CLD
<5> SIC
<4> SVAM
<3> CLC
<2>
1
0 WAT0
Address FF63H
When Reset 00H
R/W R/WNote 1
WREL WAT1
R/W
SVAM 0 1
SVA Bit to be Used as Slave Address Bits 0 to 7 Bits 1 to 7
R/W
SIC 0
INTCSI0 Interrupt Factor SelectionNote 2 CSIIF0 is set (1) upon termination of serial channel 0 transfer
1
CSIIF0 is set (1) upon bus release detection in SBI mode.
R
CLD 0 1
SCK0/SCL/P27 Pin LevelNote 3 Low Level High Level
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Notes
1. Bit 6 (CLD) is a Read-Only bit. 2. When using wake-up function, set SIC to 0. 3. When CSIE0 = 0, CLD becomes 0.
Caution
Be sure to set bits 0 to 3 to 0 when the SBI mode is used. : Slave address register
Remark SVA
CSIIF0 : Interrupt request flag supports the INTCSI0 CSIE0 : Bit 7 of the serial operating mode register 0 (CSIM0)
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(4) Various signals Figures 16-22 to 16-27 show various signals in the SBI and flag operations of the serial bus interface control register (SBIC). Table 16-5 lists various signals in SBI.
Figure 16-22. RELT, CMDT, RELD and CMDD Operations (Master)
Slave address write to SIO0 (Transfer Start Instruction) SIO0 SCK0
SB0 (SB1) RELT
CMDT
RELD
CMDD
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Figure 16-23. RELD and CMDD Operations (Slave)
Write FFH to SIO0 (Transfer start instruction)
Transfer start instruction
SIO0
A7
A6
A1
A0
SCK0
1
2
7
8
9 READY
SB0 (SB1)
A7
A6
A1
A0
ACK
Slave Address When addresses match RELD When addresses do not match CMDD
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Figure 16-24. ACKT Operation
SCK0
6
7
8
9
SB0 (SB1)
D2
D1
D0
ACK
ACK signal is output during a period of one clock immediately after setting
ACKT
When set during this period
Caution
Do not set ACKT before termination of transfer.
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Figure 16-25. ACKE Operations (a) When ACKE = 1 upon completion of transfer
SCK0 SB0 (SB1)
1
2
7
8
9
D7
D6
D2
D1
D0
ACK
ACK signal is output at 9th clock
ACKE When ACKE = 1 at this point
(b) When set after completion of transfer
SCK0 SB0 (SB1)
6
7
8
9
D2
D1
D0
ACK
ACK signal is output a period of one clock immediately after setting
ACKE
If set during this period and ACKE = 1 at the falling edge of the next SCK0
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(c) When ACKE = 0 upon completion of transfer
SCK0 SB0 (SB1)
1
2
7
8
9
D7
D6
D2
D1
D0
ACK signal is not output
ACKE When ACKE = 0 at this point
(d) When ACKE = 1 period is short
SCK0 SB0 (SB1) D2 D1 D0 ACK signal is not output
ACKE
If set and cleared during this period and ACKE = 0 at the falling edge of SCK0
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Figure 16-26. ACKD Operations (a) When ACK signal is output at 9th clock of SCK0
Transfer Start Instruction SIO0 Transfer Start SCK0 6 7 8 9
SB0 (SB1)
D2
D1
D0
ACK
ACKD
(b) When ACK signal is output after 9th clock of SCK0
Transfer Start Instruction SIO0 Transfer Start SCK0 6 7 8 9
SB0 (SB1)
D2
D1
D0
ACK
ACKD
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(c) Clear timing when transfer start is instructed in BUSY
Transfer Start Instruction SIO0
SCK0
6
7
8
9
SB0 (SB1)
D2
D1
D0
ACK
BUSY
D7
D6
ACKD
Figure 16-27. BSYE Operation
SCK0
6
7
8
9
SB0 (SB1)
D2
D1
D0
ACK
BUSY
BSYE
When BSYE = 1 at this point
If reset during this period and BSYE = 0 at the falling edge of SCK0
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Table 16-5. Various Signals in SBI Mode (1/2)
Signal Name Output Device Bus release signal (REL) Master SB0 (SB1) rising edge when SCK0 = 1
SCK0 SB0 (SB1) "H"
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Definition
Timing Chart
Output Condition
Effects on Flag
Meaning of Signal
* RELT set
* RELD set * CMDD clear
CMD signal is output to indicate that transmit data is an address. CHAPTER 16
Command signal (CMD)
Master
SB0 (SB1) falling edge when SCK0 = 1
SCK0 SB0 (SB1) "H"
* CMDT set
* CMDD set
i) Transmit data is an address after REL signal output. ii) REL signal is not output, and transmit data is a command.
SERIAL INTERFACE CHANNEL 0 (PD78014Y Subseries)
Acknowledge signal (ACK)
Master/ slave
Low-level signal to be output to SB0 (SB1) during one-clock period of SCK0 after completion of serial reception
(1) ACKE = 1 (2) ACKT set
* ACKD set
Completion of reception
Busy signal (BUSY)
Slave
[Synchronous BUSY signal] Low-level signal to be output to SB0 (SB1) following acknowledge signal
[Synchronous BUSY output]
* BSYE = 1
--
Serial receive disable because of processing
SCK0 SB0 (SB1) D0
9 ACK BUSY READY ACK BUSY READY
Ready signal (READY)
Slave
High-level signal to be output to SB0 (SB1) before serial transfer start and after completion of serial transfer
(1) BSYE = 0 (2) Execution of instruction data write SIO0 (transfer start instruction)
--
Serial receive enable
SB0 (SB1)
D0
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Signal Name Output Device Serial clock (SCK0) Master Synchronous clock to output address/command/ data, ACK signal, synchronization BUSY signal, etc. Address/command/data are transferred with the first eight synchronous clocks. Address (A7 to A0) Master 8-bit data to be transferred in synchronization with SCK0 after output of REL and CMD signals Definition Address (C7 to C0) Master 8-bit data to be transferred in synchronization with SCK0 after output of only CMD signal without REL signal output Address (D7 to D0) Master/ slave 8-bit data to be transferred in synchronization with SCK0 without output of REL and CMD signals
Table 16-5. Various Signals in SBI Mode (2/2)
Timing Chart
Output Condition
Effects on Flag
Meaning of Signal
When CSIE0 = 1, CSIIF0 set (rising Timing of signal output execution of instruction for
SCK0 1 2 7 8 9 10
edge of 9th clock of SCK0)Note 1
to serial data bus CHAPTER 16
data write to SIO0 (serial transfer
SB0 (SB1)
start instruction)
Note 2
SERIAL INTERFACE CHANNEL 0 (PD78014Y Subseries)
Address value of slave
SCK0 1 2 7 8
device on the serial bus
SB0 (SB1) REL CMD
Instruction messages to
SCK0 1 2 7 8
the slave device
SB0 (SB1) CMD
SCK0
1
2
7
8
Numeric values to be processed with slave or master device
SB0 (SB1) CMD
Notes
1. When WUP = 0, CSIIF0 is set at the rising edge of the 9th clock of SCK0. When WUP = 1, an address is received. Only when the address matches the slave address register (SVA), CSIIF0 is set (when the address does not match, RELD is cleared). 2. In BUSY state, transfer starts after the READY state is set.
CHAPTER 16
SERIAL INTERFACE CHANNEL 0 (PD78014Y Subseries)
(5) Pin configuration The serial clock pin SCK0 and serial data bus pin SB0 (SB1) have the following configurations. (a) SCK0 <2> Slave : Serial clock input/output pin : Schmitt input Both master and slave devices have an N-ch open-drain output and a Schmitt input. Because the serial data bus line has an N-ch open-drain output, an external pull-up resistor is necessary.
<1> Master : CMOS and push-pull output (b) SB0 (SB1) : Serial data input/output dual-function pin
Figure 16-28. Pin Configuration
Slave Device Master Device SCK0 Clock Output Serial Clock (Clock Input) VDD N-ch Open-Drain
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SCK0
(Clock Output) Clock Input
SB0 (SB1)
RL
SB0 (SB1)
N-ch Open-Drain SO0
SO0
Serial Data Bus
SI0
SI0
Caution Because the N-ch open-drain output must be set to high-impedance at the time of data reception, write FFH to the serial I/O shift register 0 (SIO0) in advance. However, when the wakeup function specification bit (WUP) = 1, the N-ch open-drain output will always be set to highimpedance. Thus, it is not necessary to write FFH to SIO0 before reception.
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(6) Address match detection method In the SBI mode, a particular slave device can be selected by sending a slave address from the master device. Address match detection is automatically executed by hardware. With the slave address register (SVA), and if the wake-up function specification bit (WUP) = 1, CSIIF0 is set only when the slave address transmitted from the master device matches the value set in SVA. If bit 5 (SIC) of the interrupt timing specification register (SINT) is set to 1, the wake-up function does not operate even with WUP = 1 (an interrupt request signal is generated in detecting a bus release). When the wake-up function is used, clear SIC to 0. Cautions 1. Slave selection/non-selection is detected by matching of the slave address received after bus release (RELD = 1). For this match detection, match interrupt request (INTCSI0) of the address to be generated with WUP = 1 is normally used. Thus, execute selection/non-selection detection by slave address when WUP = 1. 2. When detecting selection/non-selection without the use of interrupt request with WUP = 0, do so by means of transmission/ reception of the command preset by program instead of using the address match detection method. (7) Error detection In the SBI mode, the serial bus SB0 (SB1) status being transmitted is fetched into the destination device, that is, the serial I/O shift register 0 (SIO0). Thus, transmit errors can be detected in the following way. (a) Method of comparing SIO0 data before transmission to that after transmission In this case, if two data differ from each other, a transmit error is judged to have occurred.
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(b) Method of using the slave address register (SVA) Transmit data is set to both SIO0 and SVA and is transmitted. After termination of transmission, COI bit (match signal coming from the address comparator) of the serial operating mode register 0 (CSIM0) is tested. If it is "1", normal transmission is judged to have been carried out. If it is "0", a transmit error is judged to have occurred.
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(8) Communication operation In the SBI mode, the master device selects normally one slave device as communication target from among two or more devices by outputting an "address" to the serial bus. After the communication target device has been determined, commands and data are transmitted/received and serial communication is realized between the master and slave devices. Figures 16-29 to 16-32 show data communication timing charts. Shift operation of the serial I/O shift register 0 (SIO0) is carried out at the falling edge of serial clock (SCK0). Transmit data is latched into the SO0 latch and is output with MSB set as the first bit from the SB0/P25 or SB1/ P26 pin. Receive data input to the SB0 (or SB1) pin at the rising edge of SCK0 is latched into the SIO0.
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Program Processing Hardware Operation Transfer Line SCK0 Pin SB0 (SB1) Pin Slave Device Processing (Receiver) Program Processing Hardware Operation
Figure 16-29. Address Transmission from Master Device to Slave Device (WUP = 1)
Master Device Processing (Transmitter)
, , , ,
CMDT RELT CMDT Write Set Set Set to SIO0
Interrupt Servicing (Preparation for the Next Serial Transfer) CHAPTER 16
Serial Transmission
INTCSI0 Generation
ACKD Set
SCK0 Stop
SERIAL INTERFACE CHANNEL 0 (PD78014Y Subseries)
1
2
3
4
5
6
7
8
9
A7
A6
A5
A4
A3
A2
A1
A0
ACK
BUSY
READY
Address
, , , , , , , ,
WUP0 ACKT Set BUSY Clear
CMDD CMDD CMDD Set Clear Set RELD Set
Serial Reception
INTCSI0 Generation
ACK BUSY
Output Output
BUSY Clear
(When SVA = SIO0)
Figure 16-30. Command Transmission from Master Device to Slave Device
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,, ,, ,, ,,
CMDT Write Set to SIO0
Master Device Processing (Transmitter) Program Processing
Interrupt Servicing (Preparation for the Next Serial Transfer)
CHAPTER 16
Hardware Operation
Serial Transmission
INTCSI0 Generation
ACKD Set
SCK0 Stop
SERIAL INTERFACE CHANNEL 0 (PD78014Y Subseries)
Transfer Line SCK0 Pin
1
2
3
4
5
6
7
8
9
SB0 (SB1) Pin
C7
C6
C5
C4
C3
C2
C1
C0
ACK
BUSY
READY
Command
Slave Device Processing (Receiver) Program Processing
Hardware Operation
, , ,, ,, ,, ,, ,,
SIO0 Read
Command analysis
ACKT Set
BUSY Clear
CMDD Set
Serial Reception
INTCSI0 Generation
ACK BUSY
Output Output
BUSY Clear
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Master Device Processing (Transmitter) Program Processing Hardware Operation Transfer Line SCK0 Pin SB0 (SB1) Pin Slave Device Processing (Receiver) Program Processing Hardware Operation
Figure 16-31. Data Transmission from Master Device to Slave Device
,, ,, ,,
Write to SIO0
Interrupt Servicing (Preparation for the Next Serial Transfer)
CHAPTER 16
Serial Transmission
INTCSI0 Generation
ACKD Set
SCK0 Stop
SERIAL INTERFACE CHANNEL 0 (PD78014Y Subseries)
1
2
3
4
5
6
7
8
9
D7
D6
D5
D4 Data
D3
D2
D1
D0
ACK
BUSY
READY
,, ,, ,, ,, ,, ,, ,,
SIO0 Read ACKT Set BUSY Clear Serial Reception
INTCSI0 Generation
ACK BUSY
Output Output
BUSY Clear
Figure 16-32. Data Transmission from Slave Device to Master Device
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Master Device Processing (Receiver) Program Processing
Transfer Line
Slave Device Processing (Transmitter) Program Processing
, , , , , , , , , , , , ,
FFH Write to SIO0
SIO0 Read
ACKT FFH Write to SIO0 Set
Receive Data Processing
CHAPTER 16
Hardware Operation
SCK0 Stop
Serial Transmission
INTCSI0 Generation
ACK
Output
Serial Reception
SERIAL INTERFACE CHANNEL 0 (PD78014Y Subseries)
SCK0 Pin
1
2
3
4
5
6
7
8
9
1
2
SB0 (SB1) Pin
BUSY
READY
D7
D6
D5
D4
D3
D2
D1
D0
ACK
BUSY
READY
D7
D6
Data
Write to SIO0
Write to SIO0
Hardware Operation
BUSY Clear
Serial Reception
INTCSI0 Generation
ACKD BUSY BUSY Set Output Clear
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(9) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. * * Serial interface channel 0 operation control bit (CSIE0) = 1 Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer.
Cautions 1. If CSIE0 is set to "1" after data write to SIO0, transfer does not start. 2. Because the N-ch open-drain output must be set to high-impedance at the time of data reception, write FFH to SIO0 in advance. However, when the wake-up function specification bit (WUP) = 1, the N-ch open-drain output will always be set to high-impedance. Thus, it is not necessary to write FFH to SIO0 before reception. 3. If data is written to SIO0 when the slave is busy, the data is not lost. When the busy state is cleared and SB0 (or SB1) input is set to the high-level (READY) state, transfer starts. Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0) is set. For pins which are to be used for data input/output, be sure to carry out the following settings before serial transfer of the 1st byte after RESET input. <1> Set the P25 and P26 output latches to 1. <2> Set bit 0 (RELT) of the serial bus control register (SBIC) to 1. <3> Reset the P25 and P26 output latches from 1 to 0.
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(10) Distinction method of slave busy state When device is in the master mode, follow the method below to judge whether the slave device is in the busy state or not. <1> Detect acknowledge signal (ACK) or interrupt request signal generation. <2> Set the port mode register PM25 (or PM26) of the SB0/P25 (or SB1/P26) pin into the input mode. <3> Read out the pin state (when the pin level is high, the READY state is set). After the detection of the READY state, set the port mode register to 0 and return to the output mode.
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(11) Cautions on SBI mode (a) Slave selection/non-selection is detected by match detection of the slave address received after bus release (RELD = 1). For this match detection, match interrupt request (INTCSI0) of the address to be generated with WUP = 1 is normally used. Thus, execute selection/non-selection detection by slave address when WUP = 1. (b) When detecting selection/non-selection without the use of interrupt with WUP = 0, do so by means of transmission/reception of the command preset by program instead of using the address match detection method. (c) In the SBI mode, the BUSY signal is output until the falling of the next serial clock after the BUSY release indication. If WUP = 1 is set by mistake during this period, BUSY will not be released. Thus, after releasing BUSY, be sure to check that the SB0 (SB1) has become high level before setting WUP = 1. (d) For pins which are to be used for data input/output, be sure to carry out the following settings before serial transfer of the 1st byte after RESET input. <1> Set the P25 and P26 output latches to 1. <2> Set bit 0 (RELT) of the serial bus interface control register (SBIC) to 1. <3> Reset the P25 and P26 output latches from 1 to 0. (e) The bus release signal or the command signal is acknowledged when the SCK0 line is in high level, and the SB0 (SB1) line changes from low level to high level or from high level to low level. Thus, if the timing
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at which bus changes deviates due to effects such as board capacity, it may be determined as the bus release signal (or the command signal) even if data is sent. Therefore perform wiring carefully.
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16.4.4 2-wire serial I/O mode operation The 2-wire serial I/O mode supports any communication format by program. Communication is basically carried out with two lines of serial clock (SCK0) and serial data input/output (SB0 or SB1).
Figure 16-33. Example of Serial Bus Configuration with 2-Wire Serial I/O
VDD
VDD
Master
Slave
SCK0
SCK0
SB0 (SB1)
SB0 (SB1)
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(1) Register setting The 2-wire serial I/O mode is set with the serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC) and the interrupt timing specification register (SINT). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H.
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Symbol CSIM0
<7> CSIE0
<6> COI
<5>
4
3
2
1
0
Address FF60H
When Reset 00H
R/W R/WNote 1
WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
R/W
CSIM01 CSIM02
Serial Interface Channel 0 Clock Selection Input clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
0 1 1
x 0 1
R/W
CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27
Operating Mode
Start Bit
SI0/SB0/SDA0/ P25 Pin Function
SO0/SB1/SDA1/ SCK0/SCL/ P26 Pin Function P27 Pin Function
04 0 1
03 x 0
02
3-wire serial I/O mode (Refer to 16.4.2 3-wire serial I/O mode operation) SBI mode (Refer to 16.4.3 SBI mode operation)
Note 2 Note 2
2-wire serial 0 0 0 1 I/O mode or I2C
Note 2 Note 2
MSB
P25 (CMOS input/output) SB0/SDA0
SB1/SDA1
SCK0/SCL
1
1
0
x
x
(N-ch open-drain (N-ch openinput/output) P26 drain input/output)
bus mode 0 1
1
0
0
x
x
(N-ch open-drain (CMOS input/output) input/output)
R/W
WUP 0 1
Wake-up Function ControlNote 3 Interrupt request signal generation with each serial transfer in all modes Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1 when the SBI mode is used or when CMDD = 1 when the I2C bus mode is used) matches the slave address
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register (SVA) data in the SBI mode and I2C bus mode
R
COI 0 1
Slave Address Comparison Result FlagNote 4 Slave address register (SVA) not equal to serial I/O shift register 0 (SIC0) data Slave address register (SVA) equal to serial I/O shift register 0 (SIC0) data
R/W
CSIE0 0 1
Serial Interface Channel 0 Operation Control Operation stopped Operation enable
Notes
1. Bit 6 (COI) is a Read-Only bit. 2. Can be used freely as port function. 3. When 2-wire serial I/O mode is used, be sure to set WUP to 0. 4. When CSIE0 = 0, COI becomes 0.
Remark
x
: don't care
PMxx: Port mode register Pxx : Output latch of port
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(b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H.
Symbol SBIC R/W
<7>
<6>
<5>
<4>
<3>
<2>
<1> CMDT
<0> RELT
Address FF61H
When Reset 00H
R/W R/W
BSYE ACKD ACKE RELT
ACKT CMDD RELD
When RELT = 1, SO latch is set to 1. After SO latch setting, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
R/W
CMDT
When CMDT = 1, SO latch is cleared to 0. After SO latch clearance, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0)
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(c) Interrupt timing specification register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H.
Symbol SINT
7 0
<6> CLD
<5> SIC
<4> SVAM
<3> CLC
<2>
1
0 WAT0
Address FF63H
When Reset 00H
R/W R/WNote 1
WREL WAT1
R/W
SIC 0
INTCSI0 Interrupt Factor Selection CSIIF0 is set (1) upon termination of serial channel 0 transfer
1 R
CSIIF0 is set (1) upon bus release detection
CLD 0 1
SCK0/SCL/P27 Pin LevelNote 2 Low Level High Level
Notes
1. Bit 6 (CLD) is a Read-Only bit. 2. When CSIE0 = 0, CLD becomes 0.
Caution Remark
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Be sure to set bits 0 to 3 to 0 when 2-wire serial I/O mode is used. CSIIF0 : Interrupt request flag supports the INTCSI0 CSIE0 : Bit 7 of the serial operating mode register 0 (CSIM0)
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(2) Communication operation The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out in synchronization with the falling edge of the serial clock (SCK0). The transmit data is held in the SO0 latch and is output from the SB0/SDA0/P25 (or SB1/SDA1/P26) pin with MSB set at start. The receive data input from the SB0 (or SB1) pin is latched into the SIO0 at the rising edge of SCK0. Upon termination of 8-bit transfer, the SIO0 operation stops automatically and the interrupt request flag (CSIIF0) is set.
Figure 16-34. 2-Wire Serial I/O Mode Timings
SCK0
1
2
3
4
5
6
7
8
SB0 (SB1)
D7
D6
D5
D4
D3
D2
D1
D0
CSIIF0 End of Transfer Transfer Start at the Falling Edge of SCK0
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The SB0 (or SB1) pin specified for the serial data bus serves for N-ch open-drain input/output and thus it must be externally pulled up. Because it is necessary to be set to high-impedance the N-ch open-drain output for data reception, write FFH to SIO0 in advance. The SB0 (or SB1) pin generates the SO0 latch status and thus the SB0 (or SB1) pin output status can be manipulated by setting bit 0 (RELT) and bit 1 (CMDT) of the serial bus interface control register (SBIC). However, do not carry out this manipulation during serial transfer. Control the SCK0 pin output level in the output mode (internal system clock mode) by manipulating the P27 output latch (refer to 16.4.8 SCK0/SCL/P27 pin output manipulation).
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(3) Various signals Figure 16-35 shows RELT and CMDT operations.
Figure 16-35. RELT and CMDT Operations
SO0 Latch
RELT
CMDT
(4) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. * Serial interface channel 0 operation control bit (CSIE0) = 1 * Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer. Cautions 1. If CSIE0 is set to "1" after data write to SIO0, transfer does not start. 2. Because the N-ch open-drain output must be set to high-impedance for data reception, write FFH to SIO0 in advance. Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0) is set. (5) Error detection In the 2-wire serial I/O mode, the serial bus SB0 (SB1) status being transmitted is fetched into the destination device, that is, serial I/O shift register 0 (SIO0). Thus, transmit error can be detected in the following way. (a) Method of comparing SIO0 data before transmission to that after transmission In this case, if two data differ from each other, a transmit error is judged to have occurred. (b) Method of using the slave address register (SVA) Transmit data is set to both SIO0 and SVA and is transmitted. After termination of transmission, the COI bit (match signal coming from the address comparator) of the serial operating mode register 0 (CSIM0) is tested. If it is "1", normal transmission is judged to have been carried out. If it is "0", a transmit error is judged to have occurred.
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16.4.5 I2C bus mode operation The I2C bus mode is used when communication operations are performed between a single master device and multiple slave devices. This mode configures a serial bus that includes only a single master device, and is based on the clocked serial I/O format with the addition of bus configuration functions, which allows the master device to communicate with a number of (slave) devices using only two lines: serial clock (SCL) line and serial data bus (SDA0 or SDA1) line. Consequently, when the user plans to configure a serial bus which includes multiple microcontrollers and peripheral devices, using this configuration results in reduction of the required number of port pins and on-board wires. In the I2C bus specification, the master sends start condition, data, and stop condition signals to slave devices through the serial data bus. Slave devices automatically detect and distinguish the type of signals due to the signal detection function incorporated as hardware. This simplifies the application program to control I2C bus. An example of a serial bus configuration is shown in Figure 16-36. This system below is composed of CPUs and peripheral ICs having serial interface hardware that complies with the I2C bus specification. Note that pull-up resistors are required to connect to both serial clock line and serial data bus line, because opendrain buffers are used for the serial clock pin (SCL) and the serial data bus pin SDA0 (SDA1) on the I2C bus. The signals used in the I2C bus mode are described in Table 16-6.
Figure 16-36. Serial Bus Configuration Example Using I2C Bus
VDD VDD Master CPU Serial Clock Serial Data Bus Slave CPU1
SCL
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SCL SDA0 (SDA1)
SDA0 (SDA1)
Slave CPU2
SCL SDA0 (SDA1)
Slave IC
SCL SDA
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(1) I2C bus mode functions In the I2C bus mode, the following functions are available. (a) Automatic identification of serial data Slave devices automatically detect and identifies start condition, data, and stop condition signals sent in series through the serial data bus. (b) Chip selection by specifying device addresses The master device can select a specific slave device connected to the I2C bus and communicate with it by sending in advance the address data corresponding to the destination device. (c) Wake-up function Interrupt request occurs only if the received address equal to the value of the slave address register (SVA) during slave operation. Therefore, CPUs other than the selected slave device on the I2C bus can perform independent operations during the serial communication. (d) Acknowledge signal (ACK) control function The master device and a slave device send and receive acknowledge signals to confirm that the serial communication has been executed normally. (e) Wait signal (WAIT) control function The slave device controls a wait signal on the bus to inform the master device of the wait status. (2) I2C bus definition
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This section describes the format of serial data communications and functions of the signals used in the I2C bus mode. The transfer timings of the start condition, data, and stop condition signals, which are output onto the signal data bus of the I2C bus, are shown in Figure 16-37.
Figure 16-37. I2C Bus Serial Data Transfer Timing
SCL
1 to 7
8
9
1 to 7
8
9
1 to 7
8
9
SDA0 (SDA1) Start Address condition R/W ACK Data ACK Data ACK Stop condition
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The start condition, slave address, and stop condition signals are output by the master. The acknowledge signal (ACK) is output by either the master or the slave device (normally by the device which has received the 8-bit data that was sent). A serial clock (SCL) is continuously supplied from the master device. (a) Start condition When the SDA0 (SDA1) pin level is changed from high to low while the SCL pin is high, this transition is recognized as the start condition signal. This start condition signal, which is created using the SCL and SDA0 (or SDA1) pins, is output from the master device to slave devices to initiate a serial transfer. See section 16.4.6 Cautions on use of I2C bus mode, for details of the start condition output. The start condition signal is detected by hardware incorporated in slave devices.
Figure 16-38. Start Condition
"H" SCL
SDA0 (SDA1)
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(b) Address The 7 bits following the start condition signal are defined as an address. The 7-bit address data is output by the master device to specify a specific slave from among those connected to the bus line. Each slave device on the bus line must therefore have a different address. Therefore, after a slave device detects the start condition, it compares the 7-bit address data received and the data of the slave address register (SVA). After the comparison, only the slave device in which the data are a match becomes the communication partner, and subsequently performs communication with the master device until the master device sends a start condition or stop condition signal.
Figure 16-39. Address
SCL
1
2
3
4
5
6
7
SDA0 (SDA1)
A6
A5
A4
A3
A2
A1
A0
R/W
Address
(c) Transfer direction specification The 1-bit data that follows the 7-bit address data will be sent from the master device, and it is defined as the transfer direction specification bit. If this bit is 0, it is the master device which will send data to the slave. If it is 1, it is the slave device which
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will send data to the master.
Figure 16-40. Transfer Direction Specification
SCL
1
2
3
4
5
6
7
8
SDA0 (SDA1)
A6
A5
A4
A3
A2
A1
A0
R/W
Transfer direction specification
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(d) Acknowledge signal (ACK) The acknowledge signal indicates that the transferred serial data has definitely been received. The receiving side returns an acknowledge signal each time it receives 8-bit data. The receiving side usually outputs after it receives 8-bit data. The only exception is when the receiving side is the master device and the 8-bit data is the last transfer data; the master device outputs no acknowledge signal in this case. The sending side that has transferred 8-bit checks if the acknowledge signal has been sent from the receiving side. If the sending side device receives the acknowledge signal, which means a successful data transfer, it proceeds to the next processing. If this signal is not sent back from the slave device, this means that the data sent has not been received correctly by the slave device and therefore the master device outputs a stop condition signal to terminate subsequent transmissions.
Figure 16-41. Acknowledge Signal
SCL
1
2
3
4
5
6
7
8
9
SDA0 (SDA1)
A6
A5
A4
A3
A2
A1
A0
R/W
ACK
(e) Stop condition If the SDA0 (SDA1) pin level changes from low to high while the SCL pin is high, this transition is defined
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as a stop condition signal. The stop condition signal is output from the master to the slave device to terminate a serial transfer. The stop condition signal is detected by hardware incorporated in the slave device.
Figure 16-42. Stop Condition
"H" SCL
SDA0 (SDA1)
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(f)
Wait signal (WAIT) The wait signal is output by a slave device to inform the master device that the slave device is in wait state due to preparing for transmitting or receiving data. The slave device notifies the master device about the wait state by keeping the SCL pin low. When the wait state is released, the master device can start the next transfer. For the releasing operation of slave devices, see section 16.4.6 Cautions on use of I2C bus mode.
Figure 16-43. Wait Signal (a) Wait of 8 Clock Cycles
Slave device drives low, though master device returns to Hi-Z state. No wait is inserted after 9th clock cycle. (and before master device starts next transfer.) SCL of master device
6
7
8
9
1
2
3
4
SCL of slave device
SCL
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SDA0 (SDA1)
D2
D1
D0
ACK
D7
D6
D5
D4
Output by manipulating ACKT
(b) Wait of 9 Clock Cycles
Slave device drives low, though master device returns to Hi-Z state.
SCL of master device
6
7
8
9
1
2
3
SCL of slave device
SCL
SDA0 (SDA1)
D2
D1
D0
ACK
D7
D6
D5
Output based on the value set in ACKE in advance
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(3) Register setting The I2C bus mode setting is performed by the serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC), and the interrupt timing specify register (SINT). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets 00H.
Symbol CSIM0
<7> CSIE0
<6> COI
<5>
4
3
2
1
0
Address FF60H
When Reset 00H
R/W R/WNote 1
WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
R/W
CSIM01 CSIM02 Serial Interface Channel 0 Clock Selection 0 1 1 x 0 1 Input clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) outputNote 2 Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
R/W
CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27
Operating Mode
Start Bit
SI0/SB0/SDA0/ P25 Pin Function
SO0/SBI/SDA1/ P26 Pin Function
SCK0/SCL/ P27 Pin Function
04 0 1
03 x 0
02
3-wire serial I/O mode (Refer to 16.4.2 3-wire serial I/O mode operation) SBI mode (Refer to 16.4.3 SBI mode operation)
Note 3 Note 3
2-wire serial 0 0 0 1 I/O mode or I2C
MSB
P25 (CMOS input/output) SB0/SDA0
SB1/SDA1
SCK0/SCL
1
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1
0
x
x
(N-ch open-drain (N-ch openinput/output) P26 drain input/output)
Note 3 Note 3
bus mode 0 1
1
0
0
x
x
(N-ch open-drain (CMOS input/output) input/output)
Notes
1. Bit 6 (COI) is a Read-Only bit. 2. When the I2C bus mode is used, the clock frequency is 1/16 of the clock frequency output by TO2. 3. Can be used freely as a port.
Remark
x
: don't care
PMxx: Port mode register Pxx : Output latch of port
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R/W
WUP 0 1
Wake-up Function ControlNote 1 Interrupt request signal generation with each serial transfer in all modes Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1 when the SBI mode is used or when CMDD = 1 when the I2C bus mode is used) matches the slave address register (SVA) data in the SBI mode and the I2C bus mode
R
COI 0 1
Slave Address Comparison Result FlagNote 2 Slave address register (SVA) not equal to serial I/O shift register 0 (SIC0) data Slave address register (SVA) equal to serial I/O shift register 0 (SIC0) data
R/W
CSIE0 0 1
Serial Interface Channel 0 Operation Control Operation stopped Operation enable
Notes
1. When the wake-up function is used, set bit 5 of the interrupt timing specification register (SINT) to 0. Do not write data to serial I/O shift register 0 (SIO0) during WUP = 1. 2. When CSIE0 = 0, COI is 0.
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(b) Serial bus interface control register (SBIC) SBIC is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H.
Symbol SBIC R/W
<7>
<6>
<5>
<4>
<3>
<2>
<1> CMDT
<0> RELT
Address FF61H
When Reset 00H
R/W R/WNote
BSYE ACKD ACKE RELT
ACKT CMDD RELD
Use for stop condition output when the I2C mode is used. When RELT = 1, SO latch is set to 1. After SO latch setting, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
R/W
CMDT
Use for start condition output when the I2C mode is used. When CMDT = 1, SO latch is cleared to 0. After SO latch clearance, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
R
RELD
Stop Condition Detection Set Conditions (RELD = 1) * When stop condition is detected in the I2C bus mode
Clear Conditions (RELD = 0) * When transfer start instruction is executed * If SIO0 and SVA values do not match in address reception * When CSIE0 = 0 * When RESET input is applied
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R
CMDD
Start Condition Detection Set Conditions (CMDD = 1) * When start condition is detected in the I2C bus mode
Clear Conditions (CMDD = 0) * When transfer start instruction is executed * When stop condition is detected in the I2C bus mode * When CSIE0 = 0 * When RESET input is applied
R/W
ACKT
When the I2C bus mode is used, SDA0 (SDA1) is made low-level until the next SCL falling edge immediately after execution of the set instruction (ACKT = 1). Used to generate ACK signal by software when 8-clock wait is selected. Also cleared to 0 upon start of serial interface transfer or when CSIE0 = 0. (continued)
Note Caution Remark
Bits 2, 3, and 6 (RELD, CMDD, ACKD) are Read-Only bits. Be sure to set bit 7 to 0 when the I2C bus is used. CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0)
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R/W
ACKE 0
Acknowledge Signal Automatic Output ControlNote 1 (in the I2C bus mode) Disables acknowledge signal automatic output. (However, output with ACKT enable) Use for reception when 8-clock wait mode is selected or for transmissionNote 2.
1
Enables acknowledge signal automatic output. Outputs acknowledge signal in synchronization with the 9th clock falling edge of SCL (automatically output when ACKE = 1). However, not automatically cleared to 0 after acknowledge signal output. Used in reception with 9-clock wait mode selected.
R
ACKD
Acknowledge Detection Set Conditions (ACKD = 1)
2
Clear Conditions (ACKD = 0) * Upon execution of a transfer start instruction in the I C mode * When CSIE0 = 0 * When RESET input is applied
* When acknowledge signal is detected at the rising edge of SCL clock after completion of transfer
Notes
1. Should be set before starting transfer. 2. Output acknowledge signal in reception with ACKT when 8-clock wait is selected.
Remark
CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0)
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(c) Interrupt timing specification register (SINT) SINT is set by the 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H.
Symbol SINT
7 0
<6> CLD
<5> SIC
<4> SVAM
<3> CLC
<2>
1
0 WAT0
Address FF63H
When Reset 00H
R/W R/WNote 1
WREL WAT1
R/W
WAT1 WAT0 0 0
Wait and Interrupt ControlNote 2 Generates interrupt service request at rising edge of 8th SCK0 clock cycle. (Keeping clock output in high impedance)
0 1
1 0
Setting prohibited Used in the I2C bus mode (8-clock wait) Generates interrupt service request at rising edge of 8th SCL clock cycle. (In the case of master device, makes SCL output low to enter wait state after output. In the case of slave device, makes SCL output low to request wait pulses are input.)
1
1
Used in the I2C bus mode. (9-clock wait) Generates interrupt service request at rising edge of 9th SCL clock cycle. (In the case of master device, makes SCL output low to enter wait state after output. In the case of slave device, makes SCL output low to request waits pulses are input.)
R/W
WREL 0 1
Wait State Cancellation Control Wait state has been cancelled. Cancels wait state. Automatically cleared to 0 when the state is cancelled. (Used to cancel wait state by means of WAT0 and WAT1.)
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R/W
CLC 0
Clock Level Control Used in the I2C bus mode. Make output level of SCL pin low unless serial transfer is being performed.
1
Used in I2C bus mode. Make SCL pin enter high-impedance state unless serial transfer is being performed (except for clock line which is kept high) Use to enable master device to generate start condition and stop condition signal. (continued)
Notes
1. Bit 6 (CLD) is Read-Only bit. 2. When the I2C bus mode is used, be sure to set 1 and 0, or 1 and 1 in WAT0 and WAT1, respectively.
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R/W
SVAM 0 1
SVA Bit to be Used as Slave Address Bits 0 to 7 Bits 1 to 7
R/W
SIC 0 1
INTCSI0 Interrupt Cause SelectionNote 1 CSIIF0 is set to 1 upon termination of serial interface channel 0 transfer CSIIF0 is set to 1 upon stop condition detection in I2C bus mode
R
CLD 0 1
SCK0/SCL/P27 Pin LevelNote 2 Low level High level
Notes
1. When using the wake-up function in the I2C mode, be sure to set SIC to 1. 2. When CSIE0 = 0, CLD is 0.
Remark
SVA
: Slave address register
CSIIF0 : Interrupt request flag supports the INTCSI0 CSIE0 : Bit 7 of the serial operating mode register 0 (CSIM0)
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(4) Various signals A list of signals in the I2C bus mode is given in Table 16-6.
Table 16-6. Signals in the I2C Bus Mode
Signal name Signaled by Definition SDA0 (SDA1) falling edge when SCL is highNote 1 Signaled when CMDT is set. Affected flag(s) CMDD is set. Function Indicates that serial communication starts and subsequent data are address data. Stop condition Master SDA0 (SDA1) rising edge when SCL is highNote 1 Acknowledge signal (ACK) Master or slave Low level of SDA0 (SDA1) pin during one SCL clock cycle after serial reception Wait (WAIT) Slave Low-level signal output to SCL WAT1, WAT0 = 1x. -- Indicates state in which serial reception is not possible. Serial Clock (SCL) Address (A6 to A0) Master Master Synchronization clock for output of various signals 7-bit data synchronized with SCL immediately after start condition signal Transfer
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Start condition Master
RELT is set.
RELD is set and CMDD is cleared
Indicates end of serial transmission. Indicates completion of reception of 1 byte.
* ACKE = 1. * ACKT is set.
ACKD is set.
Execution of data write instruction to SIO0 when CSIE0 = 1 (instruction of
CSIIF0 is set.Note 3
Serial communication synchronization signal. Indicates address value for specification of slave on serial bus. Indicates whether data transmission or reception is to be performed. Contains data actually to be sent.
Master
1-bit data output in synchro- serial transfer nization with SCL after address output start)
Note 2
direction (R/W) Data (D7 to D0) Master or slave
8-bit data synchronized with SCL, not immediately after start condition
Notes
1. The level of the serial clock can be controlled by bit 3 (CLC) of the interrupt timing specification register (SINT). 2. In the wait state, the serial transfer operation will be started after the wait state is released. 3. If the 8-clock wait is selected when WUP = 0, CSIIF0 is set at the rising edge of the 8th clock cycle of SCL. If the 9-clock wait is selected when WUP = 0, CSIIF0 is set at the rising edge of the 9th clock cycle of SCL. If WUP = 1, CSIIF0 is set only when an address is received and the address matches the slave address register (SVA) value.
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(5) Pin configurations The configurations of the serial clock pin SCL and the serial data bus pins SDA0 (SDA1) are shown below. (a) SCL ......................... Pin for serial clock input/output. <1> Master ............. N-ch open-drain output <2> Slave ............... Schmitt input (b) SDA0 (SDA1) ......... Serial data input/output dual-function pin. Uses N-ch open-drain output and Schmitt-input buffers for both master and slave devices. Both serial clock and serial data bus require the external pull-up resistors to be output by N-ch open drain.
Figure 16-44. Pin Configuration
VDD Master device SCL Clock output (Clock input) SDA0 (SDA1) Data output
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Slave device
SCL VDD (Clock output) Clock input
SDA0 (SDA1)
Data output Data input
Data input
Caution Because the N-ch open-drain output must be set to high-impedance at the time of data reception, write FFH to the serial I/O shift register 0 (SIO0) in advance. However, when wakeup function is used (that is, bit 5 (WUP) of serial operating mode register 0 (CSIM0) is set), do not write FFH to SIO0 before data reception. Without writing FFH to SIO0, the N-ch open-drain output is always high-impedance state.
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(6) Address match detection method In the I2C mode, the master can select a specific slave device by sending slave address data. Address match detection is performed automatically by the slave device hardware. CSIIF0 is set only when a slave device address has a slave register (SVA), the wake-up function specification bit (WUP) is 1, and the slave address sent from the master device matches with the address set in SVA. When bit 5 (SIC) of the interrupt timing specification register (SINT) is set to 1, the wake-up function does not operate if WUP is set to 1. (In the detection of stop condition, an interrupt request signal is generated.) When wake-up function is used, clear SIC to 0. Caution Slave selection/non-selection is detected by matching of the slave address received after bus release. For this match detection, match interrupt request (INTCSI0) of the address to be generated with WUP = 1 is normally used. Thus, execute selection/non-selection detection by slave address when WUP = 1. (7) Error detection In the I2C bus mode, transmission error detection can be performed by the following methods because the serial bus SDA0 (SDA1) status during transmission is also taken into the serial I/O shift register 0 (SIO0) of the transmitting device. (a) Comparison of SIO0 data before and after transmission In this case, a transmission error is judged to have occurred if the two data values are different. (b) Using the slave address register (SVA)
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Transmit data is set in SIO0 and SVA before transmission is performed. After transmission, the COI bit (match signal from the address comparator) of serial operating mode register 0 (CSIM0) is tested: "1" indicates normal transmission, and "0" indicates a transmission error.
(8) Communication operation In the I2C bus mode, the master selects the slave device to be communicated with from among multiple devices by outputting address data onto the serial bus. After the slave address data, the master sends the R/W bit which indicates the data transfer direction, and starts serial communication with the selected slave device. Data communication timing charts are shown in Figures 16-45 and 16-46. In the transmitting device, serial I/O shift register 0 (SIO0) shifts transmission data to the SO latch in synchronization with the falling edge of the serial clock (SCL), the SO0 latch outputs the data on an MSB-first basis from the SDA0 or SDA1 pin to the receiving device. In the receiving device, the data input from the SDA0 or SDA1 pin is taken into SIO0 in synchronization with the rising edge of SCL.
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Figure 16-45. Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait) (1/3) (a) Start Condition to Address
Master device operation SIO0 Address SIO0 Address
Write SIO0 COI ACKD CMDD RELD "L" CLD P27 "H" WUP "L" ACKE "L" CMDT RELT "L" CLC WREL "L" SIC "L" INTCSI0
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Transfer line
SCL SDA0 (SDA1) Slave device operation Write SIO0 COI ACKD CMDD RELD "L" CLD P27 WUP ACKE "H" CMDT "L" RELT "L" CLC "L" WREL "L" SIC "L" INTCSI0
1
2
3
4
5
6
7
8
9
1 D7
2
3
4
5
A6 A5 A4 A3 A2 A1 A0 W ACK
D6 D5 D4
SIO0 FFH
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Figure 16-45. Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait) (2/3) (b) Data
Master device operation SIO0 Data SIO0 Data
Write SIO0 COI ACKD CMDD RELD "L" CLD P27 "H" WUP "L" ACKE "L" CMDT "L" RELT "L" CLC "L" WREL "L" SIC "L" INTCSI0
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Transfer line SCL SDA0 (SDA1) Slave device operation Write SIO0 COI ACKD CMDD RELD "L" CLD P27 WUP "L" ACKE "H" CMDT "L" RELT "L" CLC "L" WREL "L" SIC "L" INTCSI0 SIO0 FFH SIO0 FFH 1 D7 2 3 4 5 6 7 8 9 1 D7 2 3 4 5 6 7 8
D6 D5 D4 D3 D2 D1 D0 ACK
D6 D5 D4 D3 D2 D1
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Figure 16-45. Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait) (3/3) (c) Stop Condition
Master device operation SIO0 Address SIO0 Address
Write SIO0 COI ACKD CMDD RELD CLD P27 "H" WUP "L" ACKE "L" CMDT RELT CLC WREL "L" SIC "L" INTCSI0 Transfer line
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SCL SDA0 (SDA1)
1 D7
2
3
4
5
6
7
8
9
1
2
3
4
D6 D5 D4 D3 D2 D1 D0 ACK
A6 A5 A4
Slave device operationNote Write SIO0 COI ACKD CMDD RELD CLD P27 WUP ACKE "H" CMDT "L" RELT "L" CLC "L" WREL SIC "L" INTCSI0 SIO0 FFH
Note
This operation corresponds to the timing chart if it meets the specifications described in 16.4.7 (2) Avoidance. Refer to 16.4.7 (2) Limitation when used as the slave device in the I2C bus mode, for details.
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Figure 16-46. Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait) (1/3) (a) Start Condition to Address
Master device operation SIO0 Address SIO0 FFH
Write SIO0 COI ACKD CMDD RELD "L" CLD P27 "H" WUP "L" ACKE CMDT RELT "L" CLC WREL "L" SIC "L" INTCSI0
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Transfer line SCL SDA0 (SDA1) Slave device operation Write SIO0 COI ACKD CMDD RELD "L" CLD P27 WUP ACKE CMDT "L" RELT "L" CLC "L" WREL "L" SIC "L" INTCSI0 SIO0 Data 1 2 3 4 5 6 7 8 9 1 2 3 4 5
A6 A5 A4 A3 A2 A1 A0 R ACK
D7 D6 D5 D4
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Figure 16-46. Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait) (2/3) (b) Data
Master device operation SIO0 FFH SIO0 FFH
Write SIO0 COI ACKD CMDD RELD "L" CLD P27 "H" WUP "L" ACKE "H" CMDT "L" RELT "L" CLC "L" WREL "L" SIC "L" INTCSI0
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Transfer line SCL SDA0 (SDA1) Slave device operation Write SIO0 COI ACKD CMDD RELD "L" CLD P27 WUP "L" ACKE "L" CMDT "L" RELT "L" CLC "L" WREL "L" SIC "L" INTCSI0 SIO0 Data SIO0 Data 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8
D7 D6 D5 D4 D3 D2 D1 D0 ACK
D7 D6 D5 D4 D3 D2 D1
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Figure 16-46. Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait) (3/3) (c) Stop Condition
Master device operation SIO0 FFH SIO0 Address
Write SIO0 COI ACKD CMDD RELD CLD P27 "H" WUP "L" ACKE CMDT RELT CLC WREL "L" SIC "L" INTCSI0
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Transfer line SCL SDA0 (SDA1) Slave device operation Write SIO0 COI ACKD CMDD RELD CLD P27 WUP ACKE CMDT "L" RELT "L" CLC "L" WREL SIC "L" INTCSI0 SIO0 Data 1 D7 2 3 4 5 6 7 8 9 1 2 3 4
D6 D5 D4 D3 D2 D1 D0 NAK
A6 A5 A4
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(9) Start of transfer A serial transfer is started by setting transfer data in serial I/O shift register 0 (SIO0) if the following two conditions have been satisfied: * The serial interface channel 0 operation control bit (CSIE0) = 1. * After an 8-bit serial transfer, the internal serial clock is stopped or SCL is low. Cautions 1. Setting CSIE0 to 1 after writing data in SIO0 does not initiate transfer operation. 2. Because the N-ch open-drain output must be set to high-impedance at the time of data reception, write FFH to the serial I/O shift register 0 (SIO0) in advance. However, when wakeup function is used (that is, bit 5 (WUP) of serial operating mode register 0 (CSIM0) is set), do not write FFH to SIO0 before data reception. Without writing FFH to SIO0, the N-ch opendrain output is always high-impedance state. 3. If data is written to SIO0 while the slave is in the wait state, that data is held. The transfer is started when SCL is output after the wait state is cleared. When an 8-bit data transfer ends, serial transfer is stopped automatically and the interrupt request flag (CSIIF0) is set.
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16.4.6 Cautions on use of I2C bus mode (1) Start condition output (master) The SCL pin normally outputs the low-level signal when no serial clock is output. It is necessary to change the SCL pin to high in order to output a start condition signal. Set 1 in bit 3 (CLC) of the interrupt timing specification register (SINT) to drive the SCL pin high. After setting CLC, clear CLC to 0 and return the SCL pin to low. If CLC remains 1, no serial clock is output. If it is the master device which outputs the start condition and stop condition signals, confirm that CLD is set to 1 after setting CLC to 1. This is because a slave device may have set SCL to low (wait state).
Figure 16-47. Start Condition Output
SCL
SDA0 (SDA1)
CLC
CMDT
CLD
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(2) Slave wait release (slave transmission) Slave wait release operation is performed by WREL flag (bit 2 of interrupt timing specification register (SINT)) setting or execution of a serial I/O shift register 0 (SIO0) write instruction. If the slave sends data, the wait is immediately released by execution of an SIO0 write instruction and the clock rises without the start transmission bit being output in the data line. Therefore, as shown in Figure 16-48, data should be transmitted by manipulating the P27 output latch through the program. At this time, control the lowlevel width ("a" in Figure 16-48) of the first serial clock at the timing used for setting the P27 output latch to 1 after execution of an SIO0 write instruction. In addition, if the acknowledge signal from the master is not output (if data transmission from the slave is completed), set 1 in the WREL flag of SINT and release the wait. For these timings, see Figure 16-46.
Figure 16-48. Slave Wait Release (Transmission)
Master device operation
Writing FFH to SIO0
Software operation
Hardware operation
Setting Setting ACKD CSIIF0
Serial reception
Transfer line
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SCL
9
a1
2
3
SDA0 (SDA1)
A0
R
ACK
D7
D6
D5
Slave device operation P27 Write output data latch 0 to SIO0 ACK Setting output CSIIF0 Wait release P27 output latch 1
Software operation
Hardware operation
Serial transmission
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(3) Slave wait release (slave reception) Slave wait release operation is performed by WREL flag (bit 2 of interrupt timing specification register (SINT)) setting or execution of a serial I/O shift register 0 (SIO0) write instruction. When the slave receives a data, if the SCL line will immediately become high-impedance state by executing of write instruction to the SIO0, 1st bit data from the master may not be received. This is because if SCL line is being high-impedance state during execution of write instruction to the SIO0 (until next instruction execution), SIO0 does not start the operation. Therefore receive the data by manipulating the P27 output latch using program as shown in the Figure 16-49. For these timings, see Figure 16-45.
Figure 16-49. Slave Wait Release (Reception)
Master device operation Writing FFH to SIO0
Software operation
Hardware operation
Setting Setting ACKD CSIIF0
Serial transmission
Transfer line
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SCL
9
1
2
3
SDA0 (SDA1)
A0
W
ACK
D7
D6
D5
Slave device operation P27 Write output FFH latch 0 to SIO0 P27 output latch 1
Software operation
Hardware operation
ACK Setting output CSIIF0
Wait release
Serial reception
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(4) Reception completion processing by a slave During processing of reception completion by a slave device (interrupt servicing etc.), confirm the status of bit 3 (CMDD) of the serial bus interface control register (SBIC) and bit 6 (COI) of serial operating mode register 0 (CSIM0) (when CMDD = 1). This procedure is necessary to use the wake-up function normally, because if an uncertain amount of data is sent from the master device, the slave device cannot determine whether the start condition signal or data will be sent from the master. This may disable use the wake-up function. 16.4.7 Restrictions on use of I2C bus mode The PD78014Y subseries devices have the following restrictions. (1) Restriction on master device operation in the I2C bus mode Applied device:
PD78P014Y
IE-78014-R-EM
Description:
When the master device outputs the serial clock via the SCL pin, if the SCL rise time takes more than 1/32 of serial clock period, then the master device sometimes suspends serial clock output or outputs impulse signal via the SCL pin. "Rise time" is the period of time that elapses between the moment which the master device starts communication and the moment which the potential of SCL rises to 0.8VDD. Therefore a period during which the slave device outputs the wait signal by keeping the SCL pin at low level although the master device is ready for communication is included in the "rise time".
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(2) Restriction on slave device operation in the I2C bus mode Applied devices:
PD78011BY, 78012BY, 78013Y, 78014Y, 78P014Y
IE-78014-R-EM
Description:
If all of the following conditions are satisfied, all slave devices on the transfer line cannot transmit data. * The PD78014Y subseries device is used as one of the slave devices in the I2C bus mode. * The master device outputs the stop condition signal when it terminates transmission to the
PD78014Y Subseries device (i.e. slave reception).
* Following the master transmission operation to the PD78014Y Subseries device (i.e. slave reception), the master reception (i.e. slave transmission) request is sent to any unit. In the PD78014Y Subseries, communication is started by writing data in serial I/O shift register 0 (SIO0). In data reception operation, write FFH in SIO0 to be high-impedance state the N-ch open-drain output. After writing FFH into SIO0 of the PD78014Y Subseries device, if the master device drives the SCL line to high level to output the start condition or stop condition signals, then SIO0 shift operation is carried out in the PD78014Y Subseries device (slave device). As a result, written FFH is shifted and LSB of SIO0 becomes equal to the level of SDA0 (SDA1). If the master device drives SCL to high level after driving SDA0 (SDA1) to low level to output a stop condition signal as shown in the following figure, then the contents of SIO0 change to FEH (LSB = 0) according to the above-mentioned operation. Therefore the LSB of next
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reception data must be "0". The reception data which follows the start condition signal is defined as the slave address field, and the LSB of the slave address field is defined as the transfer direction specification bit. The LSB of the slave address field must be "0", so that it indicates the slave reception operation regardless of the data output from the master device.
Transfer line SCL
SDA0 (SDA1) Stop condition Slave device operation Software operation Start condition This bit must be "0".
SIO0 FFH FEH
SIO0
Change to FEH at this point
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Avoidance:
If the stop condition output timing for the PD78014Y Subseries device has been determined previously (i.e. amount of communication data between the PD78014Y Subseries device and the master device is fixed), then it is possible to avoid this restriction by software. Set bit 5 (WUP) of serial operating mode register 0 (CSIM0) and serial I/O shift register 0 (SIO0) of the slave device to 1 and FFH respectively before a stop condition signal is output. Then the wake-up function is enabled for the next slave address field which is sent from the master device, and the N-ch open-drain output is high-impedance state automatically. As a result, there is no influence on slave reception data.
Transfer line SCL
SDA0 (SDA1) Stop condition Start condition The PD78014Y subseries device does not influence this bit
Slave device operation Software operation
WUP 1
SIO0 FFH FEH
SIO0
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16.4.8 SCK0/SCL/P27 pin output manipulation The SCK0/SCL/P27 pin incorporates an output latch. Therefore, in addition to normal serial clock output, static output from this pin is also possible by controlling the output latch with an instruction. Manipulating the output latch through the software for the P27 pin, the value of serial clock can be selected by software. (SI0/SB0/SDA0 and SO0/SB1/SDA1 pins are controlled with bit 0 (RELT) or bit 1 (CMDT) of SBIC.) The SCK0/SCL/P27 pin output should be manipulated as described below. (1) In the 3-wire serial I/O mode and the 2-wire serial I/O mode Output level of SCK0/SCL/P27 pin is manipulated by the P27 output latch. <1> Set serial operating mode register 0 (CSIM0) (SCK0 pin is set in the output mode and serial operation is enabled). While serial transfer is suspended, SCK0 is set to 1. <2> Manipulate the content of the P27 output latch by executing the bit manipulation instruction.
Figure 16-50. SCK0/SCL/P27 Pin Configuration
Manipulated by the bit manipulation instruction SCK0/SCL/P27 To internal circuit P27 output latch SCK0 (1 while transfer is suspended) CSIE0 = 1 and CSIM01, CSIM00 are 1, 0 or 1, 1 respectively From serial clock control circuit
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(2) In the I2C bus mode The output level of the SCK0/SCL/P27 pin is manipulated by the CLC bit of the interrupt timing specification register (SINT). <1> Set the serial operating mode register 0 (CSIM0) (SCL pin is set in the output mode and serial operation is enabled). Set the P27 output latch to 1. While serial transfer is suspended, SCL is set to 0. <2> Manipulate the CLC bit of SINT by executing the bit manipulation instruction.
Figure 16-51. SCK0/SCL/P27 Pin Configuration
Set to 1 SCK0/SCL/P27 To internal circuit P27 output latch SCLNote CSIE0 = 1 and CSIM01, CSIM00 are 1, 0 or 1, 1 respectively From serial clock control circuit
Note
Level of SCL signal is determined by the following logic in the Figure 16-52.
Figure 16-52. SCL Signal Logic
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CLC (manipulated by the bit manipulation instruction) SCL Wait request signal Serial clock (low level while transfer is suspended)
Remarks
1. 2.
This figure shows the relationship between each signal and does not show the internal circuit. CLC: Bit 3 of the interrupt timing specification register (SINT)
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[MEMO]
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17.1 Serial Interface Channel 1 Functions Serial interface channel 1 employs the following three modes. * Operation stop mode * 3-wire serial I/O mode * 3-wire serial I/O mode with automatic transmit/receive function (1) Operation stop mode Operation stop mode is used when serial transfer is not carried out. Power consumption can be reduced. (2) 3-wire serial I/O mode (MSB-/LSB-first selectable) 3-wire serial I/O mode transfer 8-bit data with 3-wires; serial clock (SCK1), serial output (SO1), and serial input (SI1). 3-wire serial I/O mode can transfer/receive at the same time, so the data transfer processing time is fast. The start bit of 8-bit data to undergo serial transfer is switchable between MSB and LSB, so it is possible to connect to devices of any start bit. 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous clock serial interface as is the case with the 75X/XL, 78K and 17K Series. (3) 3-wire serial I/O mode with automatic transmit/receive function
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This mode with the automatic transmit/receive function added to (2) 3-wire serial I/O mode functions. The automatic transmit/receive function transfers/receives up to 32-byte data. This function enables the hardware to transmit/receive data to/from the OSD (On Screen Display) device and device with on-chip display controller/ driver independently of the CPU, thus the software load can be reduced.
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17.2 Serial Interface Channel 1 Configuration Serial interface channel 1 consists of the following hardware.
Table 17-1. Serial Interface Channel 1 Configuration
Item Register Configuration Serial I/O shift register 1 (SIO1) Automatic data transmit/receive address pointer (ADTP) Control register Timer clock select register 3 (TCL3) Serial operating mode register 1 (CSIM1) Automatic data transmit/receive control register (ADTC) Port mode register 2 (PM2)Note
Note
Refer to Figures 6-6 and 6-8 P20, P21, P23 to P26 Block Diagrams and Figures 6-7 and 6-9 P22 and P27 Block Diagrams.
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Figure 17-1. Serial Interface Channel 1 Block Diagram
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Internal Bus
Automatic Data Transmit/Receive Address Pointer (ADTP)
Buffer RAM
Internal Bus CHAPTER 17 ATE DIR Serial I/O Shift Register 1 (SIO1) DIR
RE ARLD ERCE ERR
Automatic Data Transmit Receive Control Register
TRF STRB BUSY1 BUSY0 CSIE1 DIR
Serial Operating Mode Register 1
ATE CSIM11 CSIM10
SI1/P20 PM21 SO1/P21 PM23 STB/P23 BUSY/P24
TRF Selector
SERIAL INTERFACE CHANNEL 1
P21 Output Latch
Handshake
ARLD Serial Clock Counter
Selector
INTCSI1 SIO1 Write Clear Selector TO2 Selector 4 fX/22 to fX/29
SCK1/P22
R Q S
PM22
P22 Output Latch
TCL37 TCL36 TCL35 TCL34 Timer Clock Select Register 3
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(1) Serial I/O shift register 1 (SIO1) This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO1 is set with an 8-bit memory manipulation instruction. When value in bit 7 (CSIE1) of serial operating mode register 1 (CSIM1) is 1, writing data to SIO1 starts serial operation. In transmission, data written to SIO1 is output to the serial output (SO1). In reception, data is read from the serial input (SI1) to SIO1. RESET input makes SIO1 undefined. Caution Do not write data to SIO1 while the automatic transmit/receive function is activated. (2) Automatic data transmit/receive address pointer (ADTP) This register stores the value of (the number of transmit data bytes - 1) while the automatic transmit/receive function is activated. It is decremented automatically with data transmission/reception. ADTP is set with an 8-bit memory manipulation instruction. The high-order 3 bits must be set to 0. RESET input sets ADTP to 00H. Caution Do not write data to ADTP while the automatic transmit/receive function is activated. (3) Serial clock counter This counter counts the serial clocks to be output and input during transmission/reception and to check whether 8-bit data has been transmitted/received.
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17.3 Serial Interface Channel 1 Control Registers The following three types of registers are used to control serial interface channel 1. * Timer clock select register 3 (TCL3) * Serial operating mode register 1 (CSIM1) * Automatic data transmit/receive control register (ADTC) (1) Timer clock select register 3 (TCL3) This register sets the serial clock of serial interface channel 1. TCL3 is set with an 8-bit memory manipulation instruction. RESET input sets TCL3 to 88H. Remark Besides setting the serial clock of serial interface channel 1, TCL3 sets the serial clock of serial interface channel 0.
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Figure 17-2. Timer Clock Select Register 3 Format
Symbol TCL3 7 6 5 4 3 2 1 0 Address FF43H When Reset 88H R/W R/W
TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30
TCL33
TCL32
TCL31
TCL30
Serial Interface Channel 0 Serial Clock Selection
0 0 1 1 1 1 1 1
1 1 0 0 0 0 1 1
1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1
fX/22
3
Note
fX/2 (1.25 MHz) fX/24 (625 kHz) fX/25 (313 kHz) fX/26 (156 kHz) fX/27 (78.1 kHz) fX/28 (39.1 kHz) fX/29 (19.5 kHz) Setting prohibited
Other than above
TCL37
TCL36
TCL35
TCL34
Serial Interface Channel 1 Serial Clock Selection
0 0 1
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1 1 0 0 0 0 1 1
1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1
fX/22
3
Note
fX/2 (1.25 MHz) fX/24 (625 kHz) fX/25 (313 kHz) fX/26 (156 kHz) fX/27 (78.1 kHz) fX/28 (39.1 kHz) fX/29 (19.5 kHz) Setting prohibited
1 1 1 1 1
Other than above
Note
Can be set only when the main system clock oscillate at 4.19 MHz or less.
Caution If TCL3 is to be rewritten in data other than identical data, the serial transfer must be stopped first. Remarks 1. fX: Main system clock oscillation frequency 2. Values in parentheses apply to operation with fX = 10.0 MHz
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(2) Serial operating mode register 1 (CSIM1) This register sets serial interface channel 1 serial clock, operating mode, operation enable/stop and automatic transmit/receive operation enable/stop. CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM1 to 00H.
Figure 17-3. Serial Operating Mode Register 1 Format
Symbol CSIM1 <7> CSIE1 6 DIR <5> ATE 4 0 3 0 2 0 1 0 Address FF68H When Reset 00H R/W R/W
CSIM11 CSIM10
CSIM11 CSIM10 Serial Interface Channel 1 Clock Selection 0 1 1 x 0 1 Clock externally input to SCK1 pinNote 1 8-bit timer register 2 (TM2) output Clock specified with bits 4 to 7 of timer clock select register 3 (TCL3)
ATE 0 1
Serial Interface Channel 1 Operating Mode Selection 3-wire serial I/O mode 3-wire serial I/O mode with automatic transmit/receive function
DIR 0 1
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Start Bit MSB LSB
SI1 Pin Function SI1/P20 (Input)
SO1 Pin Function SO1 (CMOS output)
CSIE CSIM PM20 P20 PM21 P21 PM22 P22
Shift Register 1 Operation
Serial Clock Counter Operation Control
SI1/P20 Pin Function
SO1/P21 Pin Function
SCK1/P22 Pin Function
1
11
Note 2 Note 2 Note 2 Note 2 Note 2 Note 2
Operation stop
Clear
P20 (CMOS input/output)
P21 (CMOS input/output) SO1
P22 (CMOS input/output) SCK1
0
x 0
x
x
x
x
x 1
x x 1 Operation enable Count operation
1
Note 3 Note 3
SI1
Note 3
1 1
x
0
0 0
(Input)
(CMOS output) (Input) SCK1 (CMOS output)
Notes
1. If the external clock input has been selected with CSIM11 set to 0, set bit 1 (BUSY1) and bit 2 (STRB) of the automatic data transmit/receive control register (ADTC) to 0 and 0, respectively. 2. Can be used freely as port function. 3. Can be used as P20 (CMOS input/output) when only transmitter is used (Set bit 7 (RE) of ADTC to 0).
Remark x Pxx
: don't care : Output latch of port
PMxx : Port mode register
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(3) Automatic data transmit/receive control register (ADTC) This register sets automatic receive enable/disable, the operating mode, strobe output enable/disable, busy input enable/disable, error check enable/disable, and displays automatic transmit/receive execution and error detection. ADTC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTC to 00H.
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Figure 17-4. Automatic Data Transmit/Receive Control Register Format
Symbol ADTC <7> RE <6> <5> <4> ERR <3> TRF <2> <1> <0> Address FF69H When Reset 00H R/W R/WNote 1
ARLD ERCE
STRB BUSY1 BUSY0 R/W
BUSY1 BUSY0 Busy Input Control 0 1 1 x 0 1 Not using busy input Busy input enable (active high) Busy input enable (active low)
R/W
STRB 0 1
Strobe Output Control Strobe output disable Strobe output enable Status of Automatic Transmit/Receive FunctionNote 2 Detection of termination of automatic transmission/reception (This bit is set to 0 upon suspension of automatic transmission/ reception or when ARLD = 0)
R
TRF 0
1
During automatic transmission/reception (This bit is set to 1 when data is written to SIO1)
R
ERR
Error Detection of Automatic Transmit/ Receive Function
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0
No error in automatic transmission/reception (This bit is set to 0 when data is written to SIO1)
1
Error occurred in automatic transmission/ reception
R/W
ERCE
Error Check Control of Automatic Transmit/ Receive Function
0
Error check disable in automatic transmission/reception
1 R/W ARLD
Error check enable (only when BUSY1 = 1) Operating Mode Selection of Automatic Transmit/Receive Function
0 1 R/W RE
Single operating mode Repetitive operating mode Receive Control of Automatic Transmit/ Receive Function
0 1
Receive disable Receive enable
Notes
1. Bits 3 and 4 (TRF and ERR) are read-only bits. 2. The termination of automatic transmission/reception should be judged by using TRF, not CSIIF1 (interrupt request flag).
Caution When an external clock input is selected with bit 1 (CSIM11) of serial operating mode register 1 (CSIM1) set to 0, set STRB and BUSY1 of ADTC to 0, 0. Remark x: don't care
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17.4 Serial Interface Channel 1 Operations The following three operating modes are available to the serial interface channel 1. * Operation stop mode * 3-wire serial I/O mode * 3-wire serial I/O mode with automatic transmit/receive function 17.4.1 Operation stop mode Serial transfer is not carried out in the operation stop mode. Thus, power consumption can be reduced. The serial I/O shift register 1 (SIO1) does not carry out shift operation either, and thus it can be used as a normal 8-bit register. In the operation stop mode, the P20/SI1, P21/SO1, P22/SCK1, P23/STB and P24/BUSY pins can be used as normal input/output ports. (1) Register setting The operation stop mode is set with the serial operating mode register 1 (CSIM1). CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM1 to 00H.
Symbol CSIM1 <7> CSIE1 6 DIR <5> ATE 4 0 3 0 2 0 1 0 Address FF68H When Reset 00H R/W R/W
CSIM11 CSIM12
CSIE CSIM PM20 P20 PM21 P21 PM22 P22
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Shift Register 1 Operation
Serial Clock Counter
SI1/P20 Pin Function
SO1/P21 Pin Function
SCK1/P22 Pin Function
1
11
Operation Control
Note 1 Note 1 Note 1 Note 1 Note 1 Note 1
Operation stop
Clear
P20 (CMOS input/output)
P21 (CMOS input/output) SO1
P22 (CMOS input/output) SCK1
0
x 0
x
x
x
x
x 1
x x 1 Operation enable Count operation
1
Note 2 Note 2
SI1
Note 2
1 1
x
0
0 0
(Input)
(CMOS output) (Input) SCK1 (CMOS output)
Notes
1. Can be used freely as port function. 2. Can be used as P20 (CMOS input/output) when only transmitter is used. (Set bit 7 (RE) of the automatic data transmit/receive control register (ADTC) to 0.)
Remark x Pxx
: don't care : Output latch of port
PMxx : Port mode register
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17.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous serial interface as is the case with the 75X/XL, 78K and 17K series. Communication is carried out with three lines of serial clock (SCK1), serial output (SO1) and serial input (SI1). (1) Register setting The 3-wire serial I/O mode is set with the serial operating mode register 1 (CSIM1). CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM1 to 00H.
Symbol CSIM1 <7> CSIE1 6 DIR <5> ATE 4 0 3 0 2 0 1 0 Address FF68H When Reset 00H R/W R/W
CSIM11 CSIM10
CSIM11 CSIM10 Serial Interface Channel 1 Clock Selection 0 1 1 x 0 1 Clock externally input to SCK1 pinNote 1 8-bit timer register 2 (TM2) output Clock specified with bits 4 to 7 of timer clock select register 3 (TCL3)
ATE 0 1
Serial Interface Channel 1 Operating Mode Selection 3-wire serial I/O mode 3-wire serial I/O mode with automatic transmit/receive function
DIR 0
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Start Bit MSB LSB
SI1 Pin Function SI1/P20 (Input)
SO1 Pin Function SO1 (CMOS output)
1
CSIE CSIM PM20 P20 PM21 P21 PM22 P22
Shift Register 1 Operation
Serial Clock Counter Operation Control
SI1/P20 Pin Function
SO1/P21 Pin Function
SCK1/P22 Pin Function
1
11
Note 2 Note 2 Note 2 Note 2 Note 2 Note 2
Operation stop
Clear
P20 (CMOS input/output)
P21 (CMOS input/output) SO1
P22 (CMOS input/output) SCK1
0
x 0
x
x
x
x
x 1
x x 1 Operation enable Count operation
1
Note 3 Note 3
SI1Note 3 (Input)
1 1
x
0
0 0
(CMOS output) (Input) SCK1 (CMOS output)
Notes
1. If the external clock input has been selected with CSIM11 set to 0, set bit 1 (BUSY1), or bit 2 (STRB) of the automatic data transmit/receive control register (ADTC) to 0, 0. 2. Can be used freely as port function. 3. Can be used as P20 (CMOS input/output) when only transmitter is used (Set bit 7 (RE) of ADTC to 0).
Remark x Pxx
: don't care : Output latch of port
PMxx : Port mode register
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(2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock. Shift operation of the serial I/O shift register 1 (SIO1) is carried out at the falling edge of the serial clock (SCK1). The transmit data is held in the SO1 latch and is output from the SO1 pin. The receive data input to the SI1 pin is latched into SIO1 at the rising edge of SCK1. Upon termination of 8-bit transfer, the SIO1 operation stops automatically and the interrupt request flag (CSIIF1) is set.
Figure 17-5. 3-Wire Serial I/O Mode Timings
SCK1
1
2
3
4
5
6
7
8
SI1
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO1
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
CSIIF1
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Transfer start synchronizing with the falling edge of SCK1 Write to SIO1
End of Transfer
Caution SO1 pin will be low by writing to SIO1.
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(3) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start at MSB or LSB. Figure 17-6 shows the configuration of the serial I/O shift register 1 (SIO1) and internal bus. As shown in the figure, MSB/LSB can be read/written in inverted form. MSB/LSB switching as the start bit can be specified with bit 6 (DIR) of the serial operating mode register 1 (CSIM1).
Figure 17-6. Circuit of Switching in Transfer Bit Order
7 6 Internal Bus 1 0 LSB Start MSB Start Read/Write Gate Read/Write Gate
SO1 Latch SI1 Shift Register 1 (SIO1) D Q
SO1
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SCK1
Start bit switching is realized by switching the bit order for data write to SIO1. The SIO1 shift order remains unchanged. Thus, switch the MSB/LSB start bit before writing data to the shift register. (4) Start of transfer A serial transfer is started by setting transfer data in the serial I/O shift register 1 (SIO1) if the following two conditions have been satisfied: * The serial interface channel 1 operation control bit (CSIE1) = 1. * After an 8-bit serial transfer, the internal serial clock is stopped or SCK1 is high. Caution Setting CSIE1 to 1 after writing data in SIO1 does not initiate transfer operation. When an 8-bit data transfer ends, serial transfer is stopped automatically and the interrupt request flag (CSIIF1) is set.
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17.4.3 3-wire serial I/O mode operation with automatic transmit/receive function This 3-wire serial I/O mode is used for transmission/reception of a maximum of 32-byte data without the use of software. Once transfer is started, the data prestored in the RAM can be transmitted by the set number of bytes, and data can be received and stored in the RAM by the set number of bytes. Handshake signals (STB and BUSY) are supported by hardware to transmit/receive data continuously. OSD (On Screen Display) LSI and peripheral LSI including LCD controller/driver can be connected without difficulty. (1) Register setting The 3-wire serial I/O mode with automatic transmit/receive function is set with the serial operating mode register 1 (CSIM1) and the automatic data transmit/receive control register (ADTC). (a) Serial operating mode register 1 (CSIM1) CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM1 to 00H.
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Symbol CSIM1
<7> CSIE1
6 DIR
<5> ATE
4 0
3 0
2 0
1
0
Address FF68H
When Reset 00H
R/W R/W
CSIM11 CSIM10
CSIM11 CSIM10 Serial Interface Channel 1 Clock Selection 0 1 1 x 0 1 Clock externally input to SCK1 pinNote 1 8-bit timer register 2 (TM2) output Clock specified with bits 4 to 7 of timer clock select register 3 (TCL3)
ATE 0 1
Serial Interface Channel 1 Operating Mode Selection 3-wire serial I/O mode 3-wire serial I/O mode with automatic transmit/receive function
DIR 0 1
Start Bit MSB LSB
SI1 Pin Function SI1/P20 (Input)
SO1 Pin Function SO1 (CMOS output)
CSIE CSIM PM20 P20 PM21 P21 PM22 P22
Shift Register 1 Operation
Serial Clock Counter Operation Control
SI1/P20 Pin Function
SO1/P21 Pin Function
SCK1/P22 Pin Function
1
11
Note 2 Note 2 Note 2 Note 2 Note 2 Note 2
Operation stop
Clear
P20 (CMOS input/output)
P21 (CMOS input/output) SO1
P22 (CMOS input/output) SCK1
0
x 0
x
x
x
x
x 1
x x 1 Operation enable Count operation
Note 3 Note 3
SI1
Note 3
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1 1
1
x
0
0 0
(Input)
(CMOS output) (Input) SCK1 (CMOS output)
Notes
1. If the external clock input has been selected with CSIM11 set to 0, set bit 1 (BUSY1) and bit 2 (STRB) of the automatic data transmit/receive control register (ADTC) to 0 and 0, respectively. 2. Can be used freely as port function. 3. Can be used as P20 (CMOS input/output) when only transmitter is used (Set bit 7 (RE) of ADTC to 0).
Remark x Pxx
: don't care : Output latch of port
PMxx : Port mode register
(b) Automatic data transmit/receive control register (ADTC) ADTC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTC to 00H.
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Symbol ADTC
<7> RE
<6>
<5>
<4> ERR
<3> TRF
<2>
<1>
<0>
Address FF69H
When Reset 00H
R/W R/WNote 1
ARLD ERCE
STRB BUSY1 BUSY0 R/W
BUSY1 BUSY0 Busy Input Control 0 1 1 x 0 1 Not using busy input Busy input enable (active high) Busy input enable (active low)
R/W
STRB 0 1
Strobe Output Control Strobe output disable Strobe output enable
R
TRF 0
Status of Automatic Transmit/Receive FunctionNote 2 Detection of termination of automatic transmission/reception (This bit is set to 0 upon suspension of automatic transmission/ reception or when ARLD = 0)
1
During automatic transmission/reception (This bit is set to 1 when data is written to SIO1)
R
ERR
Error Detection of Automatic Transmit/ Receive Function
0
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No error in automatic transmission/reception (This bit is set to 0 when data is written to SIO1)
1
Error occurred in automatic transmission/ reception
R/W
ERCE
Error Check Control of Automatic Transmit/ Receive Function
0
Error check disable in automatic transmission/reception
1 R/W
Error check enable (only when BUSY1 = 1)
ARLD
Operating Mode Selection of Automatic Transmit/Receive Function
0 1 R/W
Single operating mode Repetitive operating mode
RE
Receive Control of Automatic Transmit/ Receive Function
0
Receive disable Receive enable
Notes
1. Bits 3 and 4 (TRF and ERR) are read-only bits. 2. The termination of automatic transmission/reception
1
should be judged by using TRF, not CSIIF1 (interrupt request flag). Caution When an external clock input is selected with bit 1 (CSIM11) of the serial operating mode register 1 (CSIM1) set to 0, set STRB and BUSY1 of ADTC to 0, 0 (handshake control cannot be performed when an external clock is input). Remark x: don't care
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(2) Automatic transmit/receive data setting (a) Transmit data setting <1> Write transmit data from the least significant address FAC0H of buffer RAM (up to FADFH at maximum). However, the transmit data should be in the order from high-order address to low-order address. <2> Set to the automatic data transmit/receive address pointer (ADTP) the value obtained by subtracting 1 from the number of transmit data bytes. (b) Automatic transmit/receive mode setting <1> Set CSIE1 and ATE of the serial operating mode register 1 (CSIM1) to 1, 1. <2> Set RE of the automatic data transmit/receive control register (ADTC) to 1. <3> Write any value to the serial I/O shift register 1 (SIO1) (transfer start trigger). Caution Writing any value to SIO1 orders the start of automatic transmit/receive operation and the written value has no meaning. The following operations are automatically carried out when (a) and (b) are carried out. * After the buffer RAM data specified with ADTP is transferred to SIO1, transmission is started (start of automatic transmit/receive operation). * The received data is written to the buffer RAM address specified with ADTP. * ADTP is decremented and the next data transmission/reception is carried out. Data transmission/
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reception continues until the ADTP decremental output becomes 00H and address FAC0H data is output (end of automatic transmit/receive operation). * When automatic transmit/receive operation is terminated, TRF is cleared to 0.
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(3) Communication operation (a) Basic transmit/receive mode This transmit/receive mode is the same as the 3-wire serial I/O mode in which specified number of data are transmitted/received in 8-bit units. Serial transfer starts when any data is written to the serial I/O shift register 1 (SIO1) while the serial operating mode register 1 (CSIM1) bit 7 (CSIE1) is set to 1. Upon completion of transmission of the last byte, the interrupt request flag (CSIIF1) is set. However, the termination of automatic transmission/reception should be judged by using bit 3 (TRF) of the automatic data transmit/receive control register (ADTC), not CSIIF1. If busy control and strobe control are not executed, the P23/STB and P24/BUSY pins can be used as normal input/output ports. Figure 17-7 shows the basic transmit/receive mode operation timings, and Figure 17-8 shows the operation flowchart. In addition, Figure 17-9 shows the buffer RAM operation in 6-byte transmission/reception.
Figure 17-7. Basic Transmit/Receive Mode Operation Timings
Interval SCK1 SO1 SI1
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D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
CSIIF1
TRF
Cautions 1. Because, in the basic transmit/receive mode, the automatic transmit/receive function writes/reads data to/from the buffer RAM after 1-byte transmission/reception, an interval is inserted until the next transmission/reception. As the buffer RAM write/read is performed at the same time as CPU processing, the maximum interval is dependent upon CPU processing (see (5) Automatic data transmit/receive interval). 2. When TRF is cleared, the SO1 pin becomes low. Remark CSIIF1 : Interrupt request flag TRF : Bit 3 of the automatic data transmit/receive control register (ADTC)
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Figure 17-8. Basic Transmit/Receive Mode Flowchart
Start
Write transmit data in buffer RAM
Set ADTP to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes
Software Execution
Write any data to SIO1 (start trigger)
Write transmit data from buffer RAM to SIO1
Transmission/reception operation
Decrement pointer value
Hardware Execution
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Write receive data from SIO1 to buffer RAM
Pointer value = 0
No
Yes
TRF = 0
No Software Execution
Yes End
ADTP : Automatic data transmit/receive address pointer SIO1 TRF : Serial I/O shift register 1 : Bit 3 of automatic data transmit/receive control register (ADTC)
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In 6-byte transmission/reception (ARLD = 0, RE = 1) in basic transmit/receive mode, buffer RAM operates as follows. (i) Before transmission/reception (Refer to Figure 17-9 (a)) After any data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1. When transmission of the first byte is completed, the receive data 1 (R1) is transferred from SIO1 to the buffer RAM, and automatic data transmit/receive address pointer (ADTP) is decremented. Then transmit data 2 (T2) is transferred from the buffer RAM to SIO1. (ii) 4th byte transmission/reception point (Refer to Figure 17-9 (b)) Transmission/reception of the third byte is completed, and transmit data 4 (T4) is transferred from the buffer RAM to SIO1. When transmission of the fourth byte is completed, the receive data 4 (R4) is transferred from SIO1 to the buffer RAM, and ADTP is decremented. (iii) Completion of transmission/reception (Refer to Figure 17-9 (c)) When transmission of the sixth byte is completed, the receive data 6 (R6) is transferred from SIO1 to the buffer RAM, and the interrupt request flag (CSIIF1) is set (INTCSI1 generation).
Figure 17-9. Buffer RAM Operation in 6-Byte Transmission/Reception (in Basic Transmit/Receive Mode) (1/2) (a) Before transmission/reception
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FADFH
FAC5H
Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3)
Receive data 1 (R1)
SIO1
5 Transmit data 4 (T4) Transmit data 5 (T5) FAC0H Transmit data 6 (T6) 0 -1
ADTP
CSIIF1
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Figure 17-9. Buffer RAM Operation in 6-Byte Transmission/Reception (in Basic Transmit/Receive Mode) (2/2) (b) 4th byte transmission/reception point
FADFH
FAC5H
Receive data 1 (R1) Receive data 2 (R2) Receive data 3 (R3)
Receive data 4 (R4)
SIO1
2 Transmit data 4 (R4) Transmit data 5 (R5) FAC0H Transmit data 6 (R6) 0 -1
ADTP
CSIIF1
(c) Completion of transmission/reception
FADFH
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FAC5H
Receive data 1 (R1) Receive data 2 (R2) Receive data 3 (R3) 0 Receive data 4 (R4) Receive data 5 (R5)
SIO1
ADTP
FAC0H
Receive data 6 (R6)
1
CSIIF1
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(b) Basic transmit mode In this mode, the specified number of 8-bit unit data are transmitted. Serial transfer starts when any data is written to the serial I/O shift register 1 (SIO1) while the serial operating mode register 1 (CSIM1) bit 7 (CSIE1) is set to 1. Upon completion of transmission of the last byte, the interrupt request flag (CSIIF1) is set. However, the termination of automatic transmission/reception should be judged by using bit 3 (TRF) of the automatic data transmit/receive control register (ADTC), not CSIIF1. If receive operation, busy control and strobe control are not executed, the P20/SI1, P23/STB and P24/BUSY pins can be used as normal input/output ports. Figure 17-10 shows the basic transmission mode operation timings, and Figure 17-11 shows the operation flowchart. In addition, Figure 17-12 shows the buffer RAM operation in 6-byte transmission.
Figure 17-10. Basic Transmit Mode Operation Timings
Interval
SCK1 SO1 CSIIF1 TRF
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D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Cautions 1. Because, in the basic transmit mode, the automatic transmit/receive function reads data from the buffer RAM after 1-byte transmission, an interval is inserted until the next transmission. As the buffer RAM read is performed at the same time as CPU processing, the maximum interval is dependent upon CPU processing (see (5) Automatic data transmit/receive interval). 2. When TRF is cleared, the SO1 pin becomes low. Remark CSIIF1 : Interrupt request flag TRF : Bit 3 of the automatic data transmit/receive control register (ADTC)
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Figure 17-11. Basic Transmit Mode Flowchart
Start
Write transmit data in buffer RAM
Set ADTP to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes
Software Execution
Write any data to SIO1 (Start trigger)
Write transmit data from buffer RAM to SIO1
Decrement pointer value
Transmission operation Hardware Execution
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Pointer value = 0
No
Yes
TRF = 0
No Software Execution
Yes End
ADTP : Automatic data transmit/receive address pointer SIO1 TRF : Serial I/O shift register 1 : Bit 3 of automatic data transmit/receive control register (ADTC)
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In 6-byte transmission (ARLD = 0, RE = 0) in basic transmit mode, buffer RAM operates as follows. (i) Before transmission (Refer to Figure 17-12 (a)) After any data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1. When transmission of the first byte is completed, automatic data transmit/receive address pointer (ADTP) is decremented. Then transmit data 2 (T2) is transferred from the buffer RAM to SIO1. (ii) 4th byte transmission point (Refer to Figure 17-12 (b)) Transmission of the third byte is completed, and transmit data 4 (T4) is transferred from the buffer RAM to SIO1. When transmission of the fourth byte is completed, ADTP is decremented. (iii) Completion of transmission (Refer to Figure 17-12 (c)) When transmission of the sixth byte is completed, the interrupt request flag (CSIIF1) is set (INTCSI1 generation).
Figure 17-12. Buffer RAM Operation in 6-Byte Transmission (in Basic Transmit Mode) (1/2) (a) Before transmission
FADFH
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FAC5H
Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) 5 Transmit data 4 (T4) Transmit data 5 (T5) -1
SIO1
ADTP
FAC0H
Transmit data 6 (T6)
0
CSIIF1
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Figure 17-12. Buffer RAM Operation in 6-Byte Transmission (in Basic Transmit Mode) (2/2) (b) 4th byte transmission point
FADFH
FAC5H
Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) 2 Transmit data 4 (T4) Transmit data 5 (T5) -1
SIO1
ADTP
FAC0H
Transmit data 6 (T6)
0
CSIIF1
(c) Completion of transmission
FADFH
FAC5H
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Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) 0 Transmit data 4 (T4) Transmit data 5 (T5)
SIO1
ADTP
FAC0H
Transmit data 6 (T6)
1
CSIIF1
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(c) Repeat transmit mode In this mode, data stored in the buffer RAM is transmitted repeatedly. Serial transfer starts by writing any data to the serial I/O shift register 1 (SIO1) when 1 is set in the serial operating mode register 1 (CSIM1) bit 7 (CSIE1). Unlike the basic transmit mode, after the last byte (data in address FAC0H) has been transmitted, the interrupt request flag (CSIIF1) is not set, the value at the time when the transmission was started is set in the automatic data transmit/receive address pointer (ADTP) again, and the buffer RAM contents are transmitted again. When a reception operation, busy control and strobe control are not performed, the P20/SI1, P23/STB and P24/BUSY pins can be used as normal input/output ports. The repeat transmission mode operation timing is shown in Figure 17-13, and the operation flowchart in Figure 17-14. In addition, buffer RAM operation in 6-byte transmission in the repeat transmit mode is shown in Figure 17-15.
Figure 17-13. Repeat Transmit Mode Operation Timings
Interval SCK1 SO1 D7 D6 D5 D4 D3 D2 D1 D0
Interval
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5
Caution Because, in the repeat transmission mode, the automatic transmit/receive function reads data from the buffer RAM after 1-byte transmission, an interval is inserted until the next
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transmission. As the buffer RAM read is performed at the same time as CPU processing, the maximum interval is dependent upon CPU processing (see (5) Automatic data transmit/receive interval).
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Figure 17-14. Repeat Transmit Mode Flowchart
Start
Write transmit data in buffer RAM
Set ADTP to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes
Software Execution
Write any data to SIO1 (Start trigger)
Write transmit data from buffer RAM to SIO1
Decrement pointer value
Transmission operation Hardware Execution
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Pointer value = 0
No
Yes
Reset ADTP
ADTP : Automatic data transmit/receive address pointer SIO1 : Serial I/O shift register 1
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In 6-byte transmission (ARLD = 1, RE = 0) in the repeat transmit mode, buffer RAM operates as follows. (i) Before transmission (Refer to Figure 17-15 (a)) After any data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1. When transmission of the first byte is completed, automatic data transmit/receive address pointer (ADTP) is decremented. Then transmit data 2 (T2) is transferred from the buffer RAM to SIO1. (ii) Upon completion of transmission of 6 bytes (Refer to Figure 17-15 (b)) When transmission of the sixth byte is completed, the interrupt request flag (CSIIF1) is not set. The ADTP is set with the initial pointer value again. (iii) 7th byte transmission point (Refer to Figure 17-15 (c)) Transmit data 1 (T1) is transferred from the buffer RAM to SIO1 again. When transmission of the first byte is completed, ADTP is decremented. Then transmit data 2 (T2) is transferred from the buffer RAM to SIO1.
Figure 17-15. Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmit Mode) (1/2) (a) Before transmission
FADFH
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FAC5H
Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) 5 Transmit data 4 (T4) Transmit data 5 (T5) -1
SIO1
ADTP
FAC0H
Transmit data 6 (T6)
0
CSIIF1
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Figure 17-15. Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmit Mode) (2/2) (b) Upon completion of transmission of 6 bytes
FADFH
FAC5H
Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) 0 Transmit data 4 (T4) Transmit data 5 (T5)
SIO1
ADTP
FAC0H
Transmit data 6 (T6)
0
CSIIF1
(c) 7th byte transmission point
FADFH
FAC5H
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Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) 5 Transmit data 4 (T4) Transmit data 5 (T5) -1
SIO1
ADTP
FAC0H
Transmit data 6 (T6)
0
CSIIF1
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(d) Automatic transmission/reception suspending and restart Automatic transmission/reception can be temporarily suspended by setting bit 7 (CSIE1) of the serial operating mode register 1 (CSIM1) to 0. During 8-bit data transfer, the transmission/reception is not suspended. It is suspended upon completion of 8-bit data transfer. When suspended, bit 3 (TRF) of the automatic data transmit/receive control register (ADTC) is set to 0 after transfer of the 8th bit, and all the port pins used with the serial interface pins for dual function (P20/SI1, P21/ SO1, P22/SCK1, P23/STB and P24/BUSY) are set to the port mode. Automatic transmission/reception can be restarted and the remaining data can be transferred by setting CSIE1 to 1 and writing any data to the serial I/O shift register 1 (SIO1). Cautions 1. If the HALT instruction is executed during automatic transmission/reception, transfer is suspended and the HALT mode is set even during 8-bit data transfer. When the HALT mode is cleared, automatic transmission/reception is restarted at the suspended point. 2. When the automatic transmit/receive operation is suspended, do not change the operation mode to the 3-wire serial I/O mode while TRF = 1.
Figure 17-16. Automatic Transmission/Reception Suspension and Restart
CSIE1 = 0 (Suspended Command) Suspend Restart Command CSIE1 = 1, Write to SIO1
SCK1
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SO1 SI1
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
CSIE1: Bit 7 of the serial operating mode register 1 (CSIM1)
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(4) Synchronization control Busy control and strobe control are functions to synchronize transmission/reception between the master device and a slave device. By using these functions, a shift in bits being transmitted or received can be detected. (a) Busy control option Busy control is a function to keep the serial transmission/reception by the master device waiting while the busy signal output by a slave device to the master is active. When using this busy control option, the following conditions must be satisfied. * Bit 5 (ATE) of the serial operation mode register 1 (CSIM1) is set to 1. * Bit 1 (BUSY1) of the automatic data transmission/reception control register (ADTC) is set to 1. Figure 17-17 shows the system configuration of the master device and a slave device when the busy control option is used.
Figure 17-17. System Configuration when Busy Control Option Is Used
Master device (PD78014, 78014Y Subseries) SCK1 SO1 SI1
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Slave device SCK1 SO1 SI1
BUSY
The master device inputs the busy signal output by the slave device to the BUSY/P24 pin. The master device samples the input busy signal in synchronization with the falling of the serial clock. Even if the busy signal becomes active while 8-bit data is being transmitted or received, transmission/reception by the master is not kept waiting. If the busy signal is active at the rising edge of the serial clock 2 clocks after completion of transmission/reception of the 8-bit data, the busy input becomes valid. After that, the master transmission/ reception is kept waiting while the busy signal is active. The active level of the busy signal is set by bit 0 (BUSY0) of ADTC. BUSY0 = 0: Active high BUSY0 = 1: Active low When using the busy control option, select the internal clock as the serial clock. Control with the busy signal cannot be implemented with the external clock. Figure 17-18 shows the operation timing when the busy control option is used. Caution Busy control cannot be used simultaneously with the interval time control function of the automatic data transmission/reception interval specification register (ADTI). If used, busy control is invalid.
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Figure 17-18. Operation Timings when Using Busy Control Option (BUSY0 = 0)
SCK1 SO1 SI1 BUSY Wait CSIIF1 Busy Input Clear D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Busy Input Valid TRF
Caution When TRF is cleared, the SO1 pin becomes low. Remark CSIIF1 : Interrupt request flag TRF : Bit 3 of the automatic data transmit/receive control register (ADTC)
When the busy signal becomes inactive, waiting is released. If the sampled busy signal is inactive,
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transmission/reception of the next 8-bit data is started at the falling edge of the next clock. Because the busy signal is asynchronous with the serial clock, it takes up to 1 clock until the busy signal, even if made inactive by the slave, is sampled. It takes 0.5 clock until data transfer is started after the busy signal was sampled. To accurately release waiting, the slave must keep the busy signal inactive at least for the duration of 1.5 clock. Figure 17-19 shows the timing of the busy signal and releasing the waiting. This figure shows an example where the busy signal is active as soon as transmission/reception has been started.
Figure 17-19. Busy Signal and Wait Release (when BUSY0 = 0)
SCK1
SO1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SI1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
BUSY (active high)
1.5 clock (min.) If made inactive immediately after sampled Wait Busy input released Busy input valid
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(b) Busy & strobe control option Strobe control is a function to synchronize data transmission/reception between the master and slave devices. The master device outputs the strobe signal from the STB/P23 pin when 8-bit transmission/ receptixon has been completed. By this signal, the slave device can determine the timing of the end of data transmission. Therefore, synchronization is established even if a bit shift occurs because noise is superimposed on the serial clock, and transmission of the next byte is not affected by the bit shift. To use the strobe control option, the following conditions must be satisfied: * Bit 5 (ATE) of the serial operation mode register 1 (CSIM1) is set to 1. * Bit 2 (STRB) of the automatic data transmission/reception control register (ADTC) is set to 1. Usually, the busy control and strobe control options are simultaneously used as handshake signals. In this case, the strobe signal is output from the STB/P23 pin, and the BUSY/P24 pin is sampled, and transmission/ reception can be kept waiting while the busy signal is input. When the strobe control option is not used, the P23/STB pin can be used as a normal I/O port pin. Figure 17-20 shows the operation timing when the busy & strobe control options are used. When the strobe control option is used, the interrupt request flag (CSIIF1) that is set on completion of transmission/reception is set after the strobe signal is output.
Figure 17-20. Operation Timings when Using Busy & Strobe Control Option (BUSY0 = 0)
SCK1 SO1 SI1 STB BUSY CSIIF1 Busy Input Clear D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
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Busy Input Valid TRF
Caution When TRF is cleared, the SO1 pin becomes low. Remark CSIIF1 : Interrupt request flag TRF : Bit 3 of the automatic data transmit/receive control register (ADTC)
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(c) Bit shift detection by busy signal During automatic transmission/reception, a bit shift of the serial clock of the slave device may occur because noise is superimposed on the serial clock signal output by the master device. Unless the strobe control option is used at this time, the bit shift affects transmission of the next byte. In this case, the master can detect the bit shift by checking the busy signal during transmission by using the busy control option. A bit shift is detected by using the busy signal as follows: The slave outputs the busy signal after the rising of the eighth serial clock during data transmission/reception (to not keep transmission/reception waiting by the busy signal at this time, make the busy signal inactive within 2 clocks). The master samples the busy signal in synchronization of the falling of the leading side of the serial clock. If a bit shift does not occur, all the eight serial clocks that have been sampled are inactive. If the sampled serial clocks are active, it is assumed that a bit shift has occurred, and error processing is executed (by setting bit 4 (ERR) of the automatic transmission/reception control register (ADTC) to 1). Figure 17-21 shows the operation timing of the bit shift detection function by the busy signal.
Figure 17-21. Operation Timing of Bit Shift Detection Function by Busy Signal (when BUSY0 = 1)
SCK1 (master) Bit shift due to noise SCK1 (slave) SO1
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D7 D6 D5 D4 D3 D2 D1 D0
D7
D7 D6 D5 D4 D3 D2 D1
D0
SI1
D7 D6 D5 D4 D3 D2 D1 D0
D7
D7 D6 D5 D4 D3 D2 D1
D0
BUSY
CSIIF1
CSIE1
ERR Busy not detected Error interrupt request generated Error detected
CSIIF1 : Interrupt request flag CSIE1 : Bit 7 of serial operation mode register1 (CSIM1) ERR : Bit 4 of automatic data transmission/reception control register (ADTC)
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(5) Automatic data transmit/receive interval When the automatic data transmit/receive function is used, one byte is transmitted/received and then the read/ write operations from/to the buffer RAM are performed, therefore an interval is inserted before the next data transmission/reception. When the automatic data transmit/receive function is performed by an internal clock, since the read/write operations from/to the buffer RAM are done in parallel with CPU processing, the interval depends on the CPU processing at the moment of serial clock's eighth rising-edge timing. When the automatic data transmit/receive function is performed by an external clock, it must be chosen so that the interval may be longer than the value shown in (b).
Figure 17-22. Automatic Data Transmit/Receive Interval
Interval SCK1 SO1 SI1 CSIIF1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
CSIIF1: Interrupt request flag
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(a) In case the automatic data transmit/receive function is performed by an internal clock When bit 1 (CSIM11) of the serial operation mode register 1 (CSIM1) is set to 1, the internal clock performs. In this case, the interval is determined as follows by CPU processing.
Table 17-2. Interval by CPU Processing (in Internal Clock Operation)
CPU Processing When using multiply instruction When using divide instruction External access 1 wait mode Other than above Interval MAX. (2.5 TSCK, 26 TCPU) MAX. (2.5 TSCK, 40 TCPU) MAX. (2.5 TSCK, 18 TCPU) MAX. (2.5 TSCK, 14 TCPU)
TSCK fSCK TCPU fCPU
: 1/fSCK : Serial clock frequency : 1/fCPU : CPU clock (set by bit 0 to bit 2 (PCC0 to PCC2) of processor clock control register)
MAX. (a, b) : a or b, whichever greater
Figure 17-23. Operating Timing in Operating Automatic Transmission/Reception with Internal Clock
TCPU
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fCPU (n = 1) TSCK SCK1 SO1 SI1 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Interval
fCPU : CPU clock (set by bit 0 to bit 2 (PCC0 to PCC2) of processor clock control register (PCC)) TCPU : 1/fCPU TSCK : 1/fSCK fSCK : Serial clock frequency
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(b) In case the automatic data transmit/receive function is performed by an external clock When bit 1 (CSIM11) of the serial operation mode register 1 (CSIM1) is cleared to 0, the external clock performs. When the automatic data transmit/receive function is performed by an external clock, it must be chosen so that the interval may be longer than the value shown below.
Table 17-3. Interval by CPU Processing (in External Clock Operation)
CPU Processing When using multiply instruction When using divide instruction External access 1 wait mode Other than above Interval 26 TCPU or more 40 TCPU or more 18 TCPU or more 14 TCPU or more
TCPU : 1/fCPU fCPU : CPU clock (set by bit 0 to bit 2 (PCC0 to PCC2) of processor clock control register)
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[MEMO]
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18.1 Interrupt Function Types The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally even in a disabled state. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. It generates a standby release signal. The non-maskable interrupt has one source of interrupt request from the watchdog timer. (2) Maskable interrupts These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specify flag register (PR0L, PR0H). Multiple high priority interrupts can be applied to low priority interrupts. A standby release signal is generated. The maskable interrupt has four sources of external interrupt requests and eight sources of internal interrupt requests. (3) Software interrupt This is a vectored interrupt to be generated by executing the BRK instruction. It is acknowledged even in a
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If two or more interrupts with the same priority are
simultaneously generated, each interrupt has a predetermined priority (see Table 18-1).
disabled state. The software interrupt does not undergo interrupt priority control. 18.2 Interrupt Sources and Configuration There are total of 14 non-maskable, maskable and software interrupts in the interrupt sources (see Table 18-1).
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Table 18-1. Interrupt Source List
Interrupt Type Default PriorityNote 1 Name Interrupt Source Trigger Internal/ External Vector Table Address Non-maskable -- INTWDT Watchdog timer overflow (with watchdog timer mode 1 selected) Maskable 0 INTWDT Watchdog timer overflow (with interval timer mode selected) 1 2 3 4 5 6 7 INTP0 INTP1 INTP2 INTP3 INTCSI0 INTCSI1 INTTM3 End of serial interface channel 0 transfer End of serial interface channel 1 transfer Reference time interval signal from watch timer 8 INTTM0 16-bit timer/event counter match signal generation 9 INTTM1 8-bit timer/event counter 1 match signal generation 10 INTTM2 8-bit timer/event counter 2 match signal generation 11
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Basic Configuration TypeNote 2 (A)
Internal
0004H
(B)
Pin input edge detection
External
0006H 0008H 000AH 000CH
(C) (D)
Internal
000EH 0010H 0012H
(B)
0014H
0016H
0018H
INTAD BRK
End of A/D converter conversion Execution of BRK instruction --
001AH 003EH (E)
Software
--
Notes 1. Default priorities are intended for two or more simultaneously generated maskable interrupt requests. 0 is the highest priority and 11 is the lowest priority. 2. Basic configuration types (A) to (E) correspond to A to E in Figure 18-1.
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Figure 18-1. Basic Configuration of Interrupt Function (1/2)
(A) Internal non-maskable interrupt
Internal Bus
Interrupt Request
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
(B) Internal maskable interrupt
Internal Bus
MK
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IE
PR
ISP
Interrupt Request
IF
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
(C) External maskable interrupt (INTP0)
Internal Bus
Sampling Clock Select Register (SCS)
External Interrupt Mode Register (INTM0)
MK
IE
PR
ISP
Interrupt Request
Sampling Clock
Edge Detector
IF
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
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Figure 18-1. Basic Configuration of Interrupt Function (2/2)
(D) External maskable interrupt (except INTP0)
Internal Bus
External Interrupt Mode Register (INTM0 )
MK
IE
PR
ISP
Interrupt Request
Edge Detector
IF
Priority Control Circuit
Vector Table Address Generator
Standby Release Signal
(E) Software interrupt
Internal Bus
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Interrupt Request
Priority Control Circuit
Vector Table Address Generator
IF IE
: Interrupt request flag : Interrupt enabled flag
ISP : Inservice priority flag MK : Interrupt mask flag PR : Priority specify flag
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18.3 Interrupt Function Control Registers The following six types of registers are used to control the interrupt functions. * Interrupt request flag register (IF0L, IF0H) * Interrupt mask flag register (MK0L, MK0H) * Priority specify flag register (PR0L, PR0H) * External interrupt mode register (INTM0) * Sampling clock select register (SCS) * Program status word (PSW) Table 18-2 gives a listing of interrupt request flags, interrupt mask flags and priority specify flag names corresponding to interrupt request sources.
Table 18-2. Various Flags Corresponding to Interrupt Request Sources
Interrupt Source Interrupt Request Flag Register INTWDT INTP0 INTP1 INTP2 INTP3 INTCSI0
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Interrupt Mask Flag Register TMMK4 PMK0 PMK1 PMK2 PMK3 CSIMK0 CSIMK1 TMMK3 MK0L
Priority Specify Flag Register TMPR4 PPR0 PPR1 PPR2 PPR3 CSIPR0 CSIPR1 TMPR3 PR0L
TMIF4 PIF0 PIF1 PIF2 PIF3 CSIIF0 CSIIF1 TMIF3 TMIF0 TMIF1 TMIF2 ADIF
IF0L
INTCSI1 INTTM3 INTTM0 INTTM1 INTTM2 INTAD
IF0H
TMMK0 TMMK1 TMMK2 ADMK
MK0H
TMPR0 TMPR1 TMPR2 ADPR
PR0H
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(1) Interrupt request flag registers (IF0L, IF0H) The interrupt request flag is set to (1) when the corresponding interrupt request is generated or an instruction is executed. It is cleared to (0) when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input. IF0L and IF0H are set with a 1-bit or 8-bit memory manipulation instruction. When IF0L and IF0H are used together as a 16-bit register IF0, they are set with a 16-bit memory manipulation instruction. RESET input sets these registers to 00H.
Figure 18-2. Interrupt Request Flag Register Format
Symbol IF0L
<7>
<6>
<5>
<4> PIF3
<3> PIF2
<2> PIF1
<1> PIF0
<0> TMIF4
Address FFE0H
When Reset 00H
R/W R/W
TMIF3 CSIIF1 CSIIF0
7 IF0H 0
6 0
<5> WTIF
Note
4 0
<3> ADIF
<2>
<1>
<0> FFE1H 00H R/W
TMIF2 TMIF1 TMIF0
xxIF 0 1
Interrupt Request Flag No interrupt request signal is generated Interrupt request signal is generated and interrupt requested
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Note
WTIF flag is a test input flag. Vectored interrupt request is not generated.
Cautions 1. TMIF4 flag is R/W enabled only when a watchdog timer is used as an interval timer. If a watchdog timer mode 1 is used, set TMIF4 flag to 0. 2. Be sure to set bits 4, 6, and 7 of IF0H to 0.
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(2) Interrupt mask flag registers (MK0L, MK0H) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service and the standby clear. MK0L and MK0H are set with a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H are used together as a 16-bit register MK0, they are set with a 16-bit memory manipulation instruction. RESET input sets these registers to FFH.
Figure 18-3. Interrupt Mask Flag Register Format
Symbol MK0L <7> <6> <5> <4> <3> PMK2 <2> PMK1 <1> <0> Address FFE4H When Reset FFH R/W R/W
TMMK3 CSIMK1 CSIMK0 PMK3
PMK0 TMMK4
7 MK0H 1
6 1
<5>
WTMK
Note
4 1
<3>
<2>
<1>
<0> FFE5H FFH R/W
ADMK TMMK2 TMMK1 TMMK0
xxMK 0
Interrupt Servicing, Standby Mode Control Interrupt servicing, standby mode clear enabled
1
Interrupt servicing, standby mode clear disabled
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Note
WTMK flag controls standby mode clear enabled/disabled. The interrupt function does not control.
Cautions 1. If TMMK4 flag is read when a watchdog timer is used in watchdog timer mode 1, MK0 value becomes undefined. 2. Because port 0 is also used for the external interrupt request input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. Therefore, 1 should be set in the interrupt mask flag before using the output mode. 3. Be sure to set bits 4, 6, and 7 of MK0H to 1.
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(3) Priority specify flag registers (PR0L, PR0H) The priority specify flag is used to set the corresponding maskable interrupt priority orders. PR0L and PR0H are set with a 1-bit or 8-bit memory manipulation instruction. When PR0L and PR0H are used together as a 16-bit register PR0, they are set with a 16-bit memory manipulation instruction. RESET input sets these registers to FFH.
Figure 18-4. Priority Specify Flag Register Format
Symbol PR0L <7> <6> <5> <4> <3> PPR2 <2> PPR1 <1> <0> Address FFE8H When Reset FFH R/W R/W
TMPR3 CSIPR1 CSIPR0 PPR3
PPR0 TMPR4
7 PR0H 1
6 1
5 1
4 1
<3>
<2>
<1>
<0> FFE9H FFH R/W
ADPR TMPR2 TMPR1 TMPR0
xxPR 0 1
Priority Level Selection High priority level Low priority level
Cautions 1. When a watchdog timer is used in the watchdog timer mode 1, set the TMPR4 flag to 1. 2. Be sure to set bits 4 to 7 of PR0H to 1.
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(4) External interrupt mode register (INTM0) This register sets the valid edge for INTP0 to INTP2. INTM0 is set with an 8-bit memory manipulation instruction. RESET input sets INTM0 value to 00H. Remarks 1. INTP0 is also used for TI0/P00. 2. INTP3 is fixed at falling edge.
Figure 18-5. External Interrupt Mode Register Format
Symbol INTM0
7 ES31
6 ES30
5 ES21
4 ES20
3 ES11
2 ES10
1 0
0 0
Address FFECH
When Reset 00H
R/W R/W
ES11 0 0 1 1
ES10 0 1 0 1
INTP0 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges
ES21 0
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ES20 0 1 0 1
INTP1 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges
0 1 1
ES31 0 0 1 1
ES30 0 1 0 1
INTP2 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges
Caution
Set the valid edge for INTP0/TI0/P00 after setting bits 1 through 3 (TMC01 to TMC03) of 16-bit timer mode control register to 000 to stop the timer operation.
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(5) Sampling clock select register (SCS) This register is used to set the valid edge clock sampling clock to be input to INTP0. When remote controlled data reception is carried out using INTP0, digital noise is removed with sampling clocks. SCS is set with an 8-bit memory manipulation instruction. RESET input sets SCS to 00H.
Figure 18-6. Sampling Clock Select Register Format
Symbol SCS 7 0 6 0 5 0 4 0 3 0 2 0 1 SCS1 0 SCS0 Address FF47H When Reset 00H R/W R/W
SCS1 0 0 1 1
SCS0 0 1 0 1
INTP0 Sampling Clock Selection fX/2N+1 Setting prohibited fX/26 (156 kHz) fX/27 (78.1 kHz)
Caution
fX/2N+1 is a clock to be supplied to the CPU and fX/26 and fX/27 are clocks to be supplied to the peripheral hardware. fX/2N+1 stops in the HALT mode.
Remarks
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1. N: Value (N = 0 to 4) at bits 0 to 2 (PCC0 to PCC2) of processor clock control register (PCC) 2. fX: Main system clock oscillation frequency 3. Values in parentheses apply to operation with fX = 10.0 MHz.
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When the sampling INTP0 input level is active twice in succession, the noise eliminator sets the interrupt request flag (PIF0) to 1. Figure18-7 shows noise eliminator input/output timing.
Figure 18-7. Noise Eliminator Input/Output Timing (when rising edge is detected) (a) When input is less than the sampling cycle (tSMP)
tSMP Sampling Clock
INTP0
PIF0
"L" Because INTP0 level is not high level in sampling, PIF0 output remains at low level.
(b) When input is equal to or twice the sampling cycle (tSMP)
tSMP Sampling Clock
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INTP0
<1>
<2>
PIF0 Because sampling INTP0 level is high level twice in succession in <2>, PIF0 flag is set to 1.
(c) When input is twice or more than the sampling cycle (tSMP)
tSMP Sampling Clock
INTP0
PIF0 When INTP0 level is high level twice in succession, PIF0 flag is set to 1.
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(6) Program status word (PSW) The program status word is a register to hold the instruction execution result and the current status for interrupt request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control multiple interrupt servicing are mapped. Besides 8-bit units read/write, this register can carry out operations with a bit manipulation instruction and dedicated instructions (EI and DI). When a vectored interrupt request is acknowledged, and when the BRK instruction is executed, the contents of PSW is automatically saved into a stack and the IE flag is reset to (0). If a maskable interrupt request is acknowledged, the contents of the priority specify flag of the acknowledged interrupt are transferred to the ISP flag. The contents of acknowledged interrupt is also saved into the stack with the PUSH PSW instruction. It is reset from the stack with the RETI, RETB and POP PSW instructions. RESET input sets PSW to 02H.
Figure 18-8. Program Status Word Configuration
Symbol PSW 7 IE 6 Z 5 RBS1 4 AC 3 RBS0 2 0 1 ISP 0 CY When Reset 02H Use when normal instruction is executed ISP 0 Priority of Interrupt Currently Being Serviced High-priority interrupt servicing (low-priority interrupt disable) 1 Interrupt request not acknowledged or low priority servicing (all maskable interrupts enable)
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IE 0 1
Interrupt Request Acknowledge Enable/Disable Disable Enable
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18.4 Interrupt Servicing Operations 18.4.1 Non-maskable interrupt request acknowledge operation A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledge disable state. It does not undergo interrupt priority control and has highest priority over all other interrupts. If a non-maskable interrupt request is acknowledged, the contents of acknowledged interrupt is saved in the stacks, program status word (PSW) and program counter (PC), in that order, the IE and ISP flags are reset to 0, and the vector table contents are loaded into PC and branched. A new non-maskable interrupt request generated during execution of a non-maskable interrupt servicing program is acknowledged after the current execution of the non-maskable interrupt servicing program is terminated (following RETI instruction execution) and one main routine instruction is executed. If a new non-maskable interrupt request is generated twice or more during non-maskable interrupt service program execution, only one non-maskable interrupt request is acknowledged after termination of the non-maskable interrupt service program execution. Figure 18-9 shows the flowchart from non-maskable interrupt request generation to acknowledge. Figure 18-10 shows the non-maskable interrupt request acknowledge timing. Figure 18-11 shows the acknowledge operation if multiple non-maskable interrupt requests are generated.
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Figure 18-9. Flowchart from Non-Maskable Interrupt Request Generation to Acknowledge
Start
WDTM4 = 1 (with watchdog timer mode selected)? Yes
No Interval timer
Overflow in WDT? Yes WDTM3 = 0 (with non-maskable interrupt request selected)? Yes Interrupt request generation
No
No Reset processing
WDT interrupt servicing? Yes
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No
Interrupt request reserve
Interrupt control register unaccessed? Yes
Interrupt service start
No
WDTM WDT
: Watchdog timer mode register : Watchdog timer
Figure 18-10. Non-Maskable Interrupt Request Acknowledge Timing
PSW, PC save, jump Interrupt servicing to interrupt servicing program
CPU Processing
Instruction
Instruction
TMIF4
The interrupt request generated in this period is acknowledged at timing.
TMIF4
: Watchdog timer interrupt request flag
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Figure 18-11. Non-Maskable Interrupt Request Acknowledge Operation (a) If a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution
Main Routine
NMI request <1> NMI request <2> Execution of one instruction
NMI request <1> executed. NMI request <2> kept pending.
Pending NMI request <2> is serviced.
(b) If two non-maskable interrupt requests are newly generated during non-maskable interrupt servicing program execution
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Main Routine
NMI request <1> Execution of one instruction
NMI request <2> NMI request <3>
NMI request <1> executed. NMI request <2> kept pending. NMI request <3> kept pending.
Pending NMI request <2> is serviced.
NMI request <3> is not accepted (only one NMI request is accepted even if two or more NMI requests are generated in duplicate).
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18.4.2 Maskable interrupt request acknowledge operation A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt mask flag for that interrupt is cleared to 0. A vectored interrupt request is acknowledged in an interrupt enable state (with IE flag set to 1). However, a low-priority interrupt request is not acknowledged during high-priority interrupt service (with ISP flag reset to 0). Wait times from maskable interrupt request generation to interrupt servicing are shown in Table 18-3. Refer to Figures 18-3 and 18-4 for the interrupt request acknowledge timing.
Table 18-3. Times from Maskable Interrupt Request Generation to Interrupt Service
Maximum TimeNote 63 clocks 65 clocks
Minimum Time When XXPR = 0 When XXPR = 1 13 clocks 15 clocks
Note
If an interrupt request is generated just before a divide instruction, the wait time is maximized.
Remark
1 clock: 1/fCPU (fCPU: CPU clock)
If two or more maskable interrupt requests are generated simultaneously, the request specified for higher priority with the priority specify flag is acknowledged first. If two or more requests are specified for the same priority with the priority specify flag, the interrupt request with the higher default priority is acknowledged first. Any reserved interrupt requests are acknowledged when they become acknowledgeable. Figure 18-12 shows interrupt request acknowledge algorithms.
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If a maskable interrupt request is acknowledged, the acknowledged interrupt is saved in the stacks, program status
word (PSW) and program counter (PC), in that order, the IE flag is reset to 0, and the contents of acknowledged interrupt request priority specify flag contents are transferred to the ISP flag. Further, the vector table data determined for each interrupt request is loaded into PC and branched. Return from the interrupt is possible with the RETI instruction.
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Figure 18-12. Interrupt Request Acknowledge Processing Algorithm
Start
No
xxIF = 1?
Yes (Interrupt Request Generation)
No
Interrupt request reserve
xxMK = 0?
Yes
Yes (High Priority)
xxPR = 0?
No (Low Priority)
Any simultaneously generated xxPR = 0 interrupt requests?
Yes
Interrupt request reserve
Any highpriority interrupt among simultaneously generated xxPR = 0 interrupt requests?
Yes
Interrupt request reserve
No No IE = 1? Yes
Vectored interrupt servicing
No
Any simultaneously generated high-priority interrupt requests?
Yes
Interrupt request reserve
Interrupt request reserve
No IE = 1? No
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Yes ISP = 1? Yes
Vectored interrupt servicing
Interrupt request reserve
No
Interrupt request reserve
xxIF : Interrupt request flag xxMK : Interrupt mask flag xxPR : Priority specify flag IE ISP : Flag to control maskable interrupt request acknowledge (1 = Enable, 0 = Disable) : Flag to indicate the priority of interrupt being serviced (0 = Interrupt with high-priority is being serviced, 1 = Interrupt request is not acknowledged or an Interrupt with low-priority is being serviced)
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Figure 18-13. Interrupt Request Acknowledge Timing (Minimum Time)
12 Clocks CPU Processing Instruction Instruction
PSW, PC Save, Jump to Interrupt Servicing Interrupt Servicing Program
xxIF
(xxPR = 1) 15 Clocks
xxIF
(xxPR = 0) 13 Clocks
Remark
1 clock: 1/fCPU (fCPU: CPU clock)
Figure 18-14. Interrupt Request Acknowledge Timing (Maximum Time)
50 Clocks 12 Clocks
PSW, PC Save, Jump to Interrupt Servicing Interrupt Servicing Program
CPU Processing
Instruction
Divide Instruction
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xxIF
(xxPR = 1) 65 Clocks
xxIF
(xxPR = 0) 63 Clocks
Remark
1 clock: 1/fCPU (fCPU: CPU clock)
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18.4.3 Software interrupt request acknowledge operation A software interrupt request is acknowledged by BRK instruction execution. Software interrupt request cannot be disabled. If a software interrupt request is acknowledged, it is saved in the stacks, program status word (PSW) and program counter (PC), in that order, the IE flag is reset to 0 and the contents of the vector tables (003EH and 003FH) are loaded into PC and branched. Return from the software interrupt is possible with the RETB instruction. Caution Do not use the RETI instruction for returning from the software interrupt.
18.4.4 Multiple interrupt servicing Accepting another interrupt request while an interrupt is being serviced is called nesting interrupts. Nesting does not take place unless the interrupts (except the non-maskable interrupt) are enabled to be accepted (IE = 1). Accepting another interrupt request is disabled (IE = 0) when one interrupt has been accepted. Therefore, to enable nesting, the EI flag must be set to 1 during interrupt servicing, to enable the another interrupt. Nesting interrupts may not occur even when the interrupts are enabled. This is controlled by the priorities of the interrupts. Although two types of priorities, default priority and programmable priority, may be assigned to an interrupt, nesting is controlled by using the programmable priority. If an interrupt with the same level of priority as or the higher priority than the interrupt currently serviced occurs, that interrupt can be accepted and nested. If an interrupt with a priority lower than that of the currently serviced interrupt occurs, that interrupt cannot be accepted and nested. An interrupt that is not accepted and nested because it is disabled or it has a low priority is kept pending. This interrupt is accepted after servicing of the current interrupt has been completed and one instruction of the main routine has been executed.
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Nesting is not enabled while the non-maskable interrupt is being serviced. Table 18-4 shows the interrupts that can be nested, and Figure 18-15 shows an example of nesting.
Table 18-4. Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing
Multiple Interrupt Request Non-maskable Interrupt Request Interrupt Servicing Non-maskable interrupt Maskable interrupt ISP = 0 ISP = 1 Software interrupt N/A A A A Maskable Interrupt Request xx PR = 0 IE = 1 N/A A A A IE = 0 N/A N/A N/A N/A xx PR = 1 IE = 1 N/A N/A A A IE = 0 N/A N/A N/A N/A
Remarks
1. A N/A
: Multiple interrupt enable : Multiple interrupt disable
2. ISP and IE are flags included in PSW. ISP = 0 : High-priority interrupt servicing ISP = 1 : Interrupt request is not acknowledged or low-priority interrupt servicing IE = 0 IE = 1 : Interrupt request acknowledge disabled : Interrupt request acknowledge enabled
3. xxPR is a flag included in PR0L, PR0H. xxPR = 0: High-priority level xxPR = 1: Low-priority level
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Figure 18-15. Multiple Interrupt Examples (1/2)
Example 1. Two multiple interrupts are generated
Main Processing
INTxx Servicing IE = 0 EI INTyy (PR = 0) IE = 0
INTyy Servicing IE = 0 EI INTzz (PR = 0)
INTzz Servicing
EI
INTxx (PR = 1)
RETI
RETI
RETI
During interrupt INTxx servicing, two interrupt requests, INTyy and INTzz are acknowledged, and a multiple interrupt is generated. An EI instruction is issued before each interrupt request acknowledge, and the interrupt request acknowledge enable state is set. Example 2. Multiple interrupt is not generated by priority control
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Main Processing
INTxx Servicing
INTyy Servicing
EI
IE = 0 EI INTyy (PR = 1) RETI
INTxx (PR = 0)
1 Instruction Execution
IE = 0
RETI
The interrupt request INTyy generated during interrupt INTxx servicing is not acknowledged because the interrupt priority is lower than that of INTxx, and a multiple interrupt is not generated. INTyy request is retained and acknowledged after execution of 1 instruction execution of the main processing. PR = 0 : High-priority level PR = 1 : Low-priority level IE = 0 : Interrupt request acknowledge disabled
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Figure 18-15. Multiple Interrupt Example (2/2)
Example 3. A multiple interrupt is not generated because interrupts are not enabled
Main Processing IE = 0 EI INTyy (PR = 0)
INTxx Servicing
INTyy Servicing
INTxx (PR = 0)
RETI
1 Instruction Execution
IE = 0
RETI
Because interrupts are not enabled in interrupt INTxx servicing (an EI instruction is not issued), interrupt request INTyy is not acknowledged, and a multiple interrupt is not generated. The INTyy request is reserved and
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acknowledged after 1 instruction execution of the main processing. PR = 0 : High-priority level IE = 0 : Interrupt request acknowledge disabled
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18.4.5 Interrupt request reserve Some instructions may reserve the acknowledge of an instruction request until the completion of the execution of the next instruction even if the interrupt request is generated during the execution. The following shows such instructions (interrupt request reserve instruction). * MOV * MOV * MOV * MOV1 * MOV1 * AND1 * OR1 * XOR1 * SET1 * CLR1 * RETB * RETI * PUSH * POP * BT * BF * EI * DI
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PSW, #byte A, PSW PSW, A PSW.bit, CY CY, PSW.bit CY, PSW.bit CY, PSW.bit CY, PSW.bit PSW.bit PSW.bit
PSW PSW PSW.bit, $addr16 PSW.bit, $addr16
* BTCLR PSW.bit, $addr16
* Manipulation instructions for IF0L, IF0H, MK0L, MK0H, PR0L, PR0H and INTM0 registers BRK instruction is not an interrupt request reserve instruction described above. However, in a software interrupt started by the execution of BRK instruction, the IE flag is cleared to 0. Therefore, interrupt requests are not acknowledged even when a maskable interrupt request is issued during the execution of the BRK instruction. However, non-maskable interrupt requests are acknowledged. Figure 18-16 shows the interrupt request reserve timing.
Caution
Figure 18-16. Interrupt Request Reserve
PSW, PC Save, Jump to Interrupt Servicing Interrupt Servicing Program
CPU Processing
Instruction N
Instruction M
xxIF
Remarks
1. Instruction N : Interrupt request reserve instruction 2. Instruction M : Instruction except interrupt reserve instructions 3. Operation of xxIF (interrupt request) is not affected by xxPR (priority level) value.
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18.5 Test Function In this function, when the watch timer overflows and when a rising edge of port 4 is detected, the corresponding test input flag is set (1), and a standby release signal is generated. Unlike the interrupt function, vectored processing not performed. There are two test input sources as listed in Table 18-5. Basic configuration is shown in Figure 18-17.
Table 18-5. Test Input Source
Test Input Source Name INTWT INTPT4 Trigger Watch timer overflow Falling edge detection of Port 4 Internal External Internal/External
Figure 18-17. Basic Configuration of Test Function
Internal Bus
MK
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Test Input Signal
IF
Standby Release Signal
IF
: Test Input Flag
MK : Test Mask Flag 18.5.1 Test function control registers The following three types of registers are used to control the test functions. * Interrupt request flag register 0H (IF0H) * Interrupt mask flag register 0H (MK0H) * Key return mode register (KRM)
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Names of test input flag and test mask flag corresponding to test input signal name are shown in Table 18-6.
Table 18-6. Various Flags Corresponding to Test Input Signal
Test Input Signal Name INTWT INTPT4 Test Input Flag WTIF KRIF Test Mask Flag WTMK KRMK
(1) Interrupt request flag register 0H (IF0H) This register displays the watch timer overflow detection/non-detection. IF0H is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets IF0H to 00H.
Figure 18-18. Interrupt Request Flag Register 0H Format
Symbol IF0H 7 0 6 0 <5> WTIF 4 0 <3> ADIF <2> <1> <0> Address FFE1H When Reset 00H R/W R/W
TMIF2 TMIF1 TMIF0
WTIF 0 1
Watch timer overflow detection flag Non detection Detection
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Caution
Be sure to set bits 4, 6, and 7 to 0.
(2) Interrupt mask flag register 0H (MK0H) This register sets standby mode clear enable/disable by watch timer. MK0H is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets MK0H to FFH.
Figure 18-19. Interrupt Mask Flag Register 0H Format
Symbol MK0H 7 1 6 1 <5> WTMK 4 1 <3> <2> <1> <0> Address FFE5H When Reset FFH R/W R/W
ADMK TMMK2 TMMK1 TMMK0
WTMK 0 1
Standby mode control by watch timer Standby mode clear enabled Standby mode clear disabled
Caution
Be sure to set bits 4, 6, and 7 to 1.
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(3) Key return mode register (KRM) This register set the standby mode clear enable/disable with the key return signal (falling edge detection of Port 4). KRM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets KRM to 02H.
Figure 18-20. Key Return Mode Register Format
Symbol KRM 7 0 6 0 5 0 4 0 3 0 2 0 <1> KRMK <0> KRIF Address FFF6H When Reset 02H R/W R/W
KRIF 0 1
Key return signal detection flag Non detection Detection (falling edge detection of Port 4)
KRMK 0 1
Standby mode control with key return signal Standby mode clear enabled Standby mode clear disabled
Caution
When falling edge detection is used in Port 4, take care to clear KRIF to 0 (KRIF is not automatically cleared to 0).
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18.5.2 Test input signal acknowledge operation (1) Internal test input signal An internal test input signal (INTWT) is generated when the watch timer overflows and the WTIF flag is set by it. At this time, the standby release signal is generated if it is not masked by the interrupt mask flag (WTMK). By checking the WTIF flag in a cycle shorter than the overflow cycle of the watch timer, the watch function can be effected. (2) External test input signal If a falling edge is input to a pin of port 4 (P40 to P47), an external test input signal (INTP4) is generated, setting the KRIF flag. At this time, the standby release signal is generated if it is not masked by the interrupt mask flag (KRMK). By using port 4 for key return signal input of a key matrix, the presence or absence of a key input can be checked by the status of the KRIF flag.
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[MEMO]
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EXTERNAL DEVICE EXPANSION FUNCTION
CHAPTER 19
EXTERNAL DEVICE EXPANSION FUNCTION
19.1 External Device Expansion Functions The external device expansion functions are intended to connect external devices to areas other than the internal ROM, RAM and SFR. Connection of external devices uses port 4 to port 6. Port 4 to port 6 control address/data, read/write strobe, wait, address strobe, etc.
Table 19-1. Pin Functions in External Memory Expansion Mode
Pin Function at External Device Connection Name AD0 to AD7 A8 to A15 RD WR WAIT ASTB Function Multiplexed address/data bus Address bus Read strobe signal Write strobe signal Wait signal Address strobe signal Alternate Function P40 to P47 P50 to P57 P64 P65 P66 P67
Table 19-2. State of Port 4 to Port 6 Pins in External Memory Expansion Mode
Port
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Port 4 0 to 7
Port 5 0 1 2 3 4 5 6 7
Port 6 0 1 2 3 4 5 6 7
External Expansion Mode Single-chip mode 256 bytes expansion mode 4 Kbytes expansion mode 16 Kbytes expansion mode Full-address mode
Port Address/Data
Port Port
Port Port RD, WR, WAIT, ASTB
Address/Data
Address
Port
Port
RD, WR, WAIT, ASTB
Address/Data
Address
Port
Port
RD, WR, WAIT, ASTB
Address/Data
Address
Port
RD, WR, WAIT, ASTB
Caution
When the external wait function is not used, the WAIT pin can be used as a port in all modes.
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Memory maps when using the external device expansion function are as follows.
Figure 19-1. Memory Map when Using External Device Expansion Function (1/2) (a) PD78011B, 78011BY Memory Map
FFFFH SFR FF00H FEFFH Internal High-speed RAM FD00H FCFFH Reserved FAE0H FADFH FAC0H FABFH FA80H FA7FH Buffer RAM FAE0H FADFH FAC0H FABFH FA80H FA7FH Buffer RAM FD00H FCFFH Reserved FF00H FEFFH Internal High-speed RAM
(b) PD78012B, 78012BY Memory Map
FFFFH SFR
Reserved
Reserved
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Full-address mode (when MM2 to MM0 = 111) Full-address mode (when MM2 to MM0 = 111)
8000H 7FFFH 6000H 5FFFH 16 Kbytes expansion mode (when MM2 to MM0 = 101) 3000H 2FFFH 4 Kbytes expansion mode (when MM2 to MM0 = 100) 2100H 20FFH 2000H 1FFFH 4100H 40FFH 4000H 3FFFH 256 bytes expansion mode (when MM2 to MM0 = 011) Single-chip mode Single-chip mode 0000H 0000H 5000H 4FFFH 4 Kbytes expansion mode (when MM2 to MM0 = 100) 16 Kbytes expansion mode (when MM2 to MM0 = 101)
256 bytes expansion mode (when MM2 to MM0 = 011)
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Figure 19-1. Memory Map when Using External Device Expansion Function (2/2) (a) PD78013, 78013Y Memory Map (b) PD78014, 78014Y, 78P014, 78P014Y Memory Map
FFFFH SFR FF00H FEFFH FF00H FEFFH SFR
FFFFH
Internal High-speed RAM
Internal High-speed RAM
FB00H FAFFH Reserved FAE0H FADFH Buffer RAM FAC0H FABFH Reserved FA80H FA7FH
FB00H FAFFH Reserved FAE0H FADFH Buffer RAM FAC0H FABFH Reserved FA80H FA7FH Full-address mode (when MM2 to MM0 = 111)
Full-address mode (when MM2 to MM0 = 111)
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C000H BFFFH A000H 9FFFH 16 Kbytes expansion mode (when MM2 to MM0 = 101) 7000H 6FFFH 4 Kbytes expansion mode (when MM2 to MM0 = 100) 6100H 60FFH 6000H 5FFFH 8100H 80FFH 8000H 7FFFH 9000H 8FFFH 4 Kbytes expansion mode (when MM2 to MM0 = 100) 16 Kbytes expansion mode (when MM2 to MM0 = 101)
256 bytes expansion mode (when MM2 to MM0 = 011)
256 bytes expansion mode (when MM2 to MM0 = 011)
Single-chip mode Single-chip mode
0000H
0000H
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19.2 External Device Expansion Control Register The external device expansion function is controlled by the memory expansion mode register (MM). MM sets the wait count and external expansion area. MM also sets the input/output of port 4. MM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 10H.
Figure 19-2. Memory Expansion Mode Register Format
Symbol MM 7 0 6 0 5 PW1 4 PW0 3 0 2 MM2 1 MM1 0 MM0 Address FFF8H When Reset 10H R/W R/W
MM2
MM1
MM0
Single-chip/Memory
P40 to P47, P50 to P57, P64 to P67 Pins Condition P50 to P53 Port mode P54, P55 P56, P57 P64 to P67
Expansion Mode Selection P40 to P47 0 0 0 0 0 1 0 1 1 Memory expansion 1 0 0 mode 256 bytes mode 4 Kbytes mode 1 0 1 16 Kbytes mode 1
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Single-chip mode
Port
Input
mode Output AD0 to AD7 Port mode P64 = RD P65 = WR A8 to A11 Port mode P66 = WAIT P67 = ASTB A12, A13 Port mode
1
1
Full-address modeNote
A14, A15
Other than above
Setting prohibited
PW1 0 0 1 1
PW0 0 1 0 1
Wait Control Without wait With wait (1 wait state insertion) Setting prohibited Wait control with an external wait pin
Note
The full-address mode allows external expansion to the entire 64 Kbytes address space except for the internal ROM, RAM and SFR areas and the reserved areas.
Remark
P60 to P63 pins enter the port mode regardless of the single-chip mode or memory expansion mode.
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19.3 External Device Expansion Function Timing Timing control signal output pins in the external memory expansion mode are as follows. (1) RD pin (Alternate function: P64) Read strobe signal output pin. The read strobe signal is output in data access and instruction fetch from external memory. During internal memory access, the read strobe signal is not output (maintains high level). (2) WR pin (Alternate function: P65) Write strobe signal output pin. The write strobe signal is output in data access to external memory. During internal memory access, the write strobe signal is not output (maintains high level). (3) WAIT pin (Alternate function: P66) External wait signal input pin. When the external wait function is not used, the WAIT pin can be used as an input/ output port. During internal memory access, the external wait signal is ignored. (4) ASTB pin (Alternate function: P67) Address strobe signal output pin. Timing signal is always output regardless of the data access or instruction fetch from external memory. The address strobe signal is also output when the internal memory is accessed. (5) AD0 to AD7, A8 to A15 pins (Alternate function: P40 to P47, P50 to P57) Address/data signal output pins. Valid signals are output or input during instruction fetch and data access from/
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to external memory. These signals change when the internal memory is accessed (output values are undefined). Timing charts are shown in Figures 19-3 to 19-6.
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Figure 19-3. Instruction Fetch from External Memory (a) When without Wait (PW1, PW0 = 0, 0) Setup
ASTB RD AD0 to AD7 A8 to A15
Low-order address Instruction code
High-order address
(b) When with Wait (PW1, PW0 = 0, 1) Setup
ASTB RD AD0 to AD7 A8 to A15 Internal wait signal (1-clock wait)
Low-order address
Instruction code High-order address
(c) When External Wait (PW1, PW0 = 1, 1) Setup
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ASTB RD AD0 to AD7 A8 to A15 WAIT
Low-order address
Instruction code High-order address
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Figure 19-4. External Memory Read Timing (a) When without Wait (PW1, PW0 = 0, 0) Setup
ASTB RD AD0 to AD7 A8 to A15
Low-order address
Read data High-order address
(b) When with Wait (PW1, PW0 = 0, 1) Setup
ASTB RD AD0 to AD7 A8 to A15 Internal wait signal (1-clock wait)
Low-order address
Read data High-order address
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(c) When External Wait (PW1, PW0 = 1, 1) Setup
ASTB RD AD0 to AD7 A8 to A15 WAIT
Low-order address
Read data High-order address
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Figure 19-5. External Memory Write Timing (a) When without Wait (PW1, PW0 = 0, 0) Setup
ASTB WR AD0 to AD7 A8 to A15
Low-order address
Hi-Z High-order address
Write data
(b) When with Wait (PW1, PW0 = 0, 1) Setup
ASTB WR AD0 to AD7 A8 to A15 Internal wait signal (1-clock wait)
Low-order address
Hi-Z High-order address
Write data
(c) When External Wait (PW1, PW0 = 1, 1) Setup
ASTB
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WR AD0 to AD7 A8 to A15 WAIT
Low-order address
Hi-Z
Write data High-order address
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Figure 19-6. External Memory Read Modify Write Timing (a) When without Wait (PW1, PW0 = 0, 0) Setup
ASTB RD WR AD0 to AD7 A8 to A15
Low-order address Read data Write data
High-order address
(b) When with Wait (PW1, PW0 = 0, 1) Setup
ASTB RD WR AD0 to AD7 A8 to A15 Internal wait signal (1-clock wait)
Low-order address
Read data
Write data
High-order address
(c) When External Wait (PW1, PW0 = 1, 1) Setup
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ASTB RD WR AD0 to AD7 A8 to A15 WAIT
Low-order address
Read data High-order address
Write data
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19.4 Example of Memory Connection An example of external memory connection with the PD78014 is shown in Figure 19-7. SRAM is used as the external memory in this application example. In addition, the external device expansion function is used in the fulladdress mode, and the internal ROM is allocated to addresses 0000H to 7FFFH (32 Kbytes), and SRAM is allocated to addresses above 8000H.
Figure 19-7. Example of Memory Connection with PD78014
VDD
PD43256B
PD78014
CS Data bus RD WR Address bus A8 to A14
PD74HC573
OE WE I/O1 to I/O8 A0 to A14
ASTB
LE Q0 to Q7
AD0 to AD7
D0 to D7 OE
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Caution
At the external memory read modify write timing, the time from RD signal rising to write data output is very short, so that the write data sometimes conflicts with the output data from external memory (SRAM, etc). In this case, it is possible to avoid data conflict by not using the following instructions which generate read modify write timing. XCH XCH XCH XCH XCH A, !addr16 A, [DE] A, [HL] A, [HL + byte] A, [HL + B] XCH MOV1 SET1 CLR1 BTCLR A, [HL + C] [HL].bit, CY [HL].bit [HL].bit [HL].bit, $addr16
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STANDBY FUNCTION
CHAPTER 20
STANDBY FUNCTION
20.1 Standby Function and Configuration 20.1.1 Standby function The standby function is intended to decrease the power consumption of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock. System clock oscillator continues oscillation. In this mode, current consumption cannot be decreased as in the STOP mode. The HALT mode is valid to restart immediately upon interrupt request and to carry out intermittent operations like watch operations. (2) STOP mode STOP instruction execution sets the STOP mode. In the STOP mode, the main system clock oscillator stops and the whole system stops. CPU current consumption can be considerably decreased. Data memory low-voltage hold (down to VDD = 2 V) is possible. Thus, the STOP mode is effective to hold data memory contents with ultra-low current consumption. Because this mode can be cleared upon interrupt request, it enables intermittent operations to be carried out. However, because a wait time is necessary to secure an oscillation stabilization time after the STOP mode is cleared, select the HALT mode if it is necessary to start processing immediately upon interrupt request.
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In any mode, all the contents of the register, flag and data memory just before standby mode setting are held. The input/output port output latch and output buffer statuses are also held. Cautions 1. The STOP mode can be used only when the system operates with the main system clock (subsystem clock oscillation cannot be stopped). The HALT mode can be used with either the main system clock or the subsystem clock. 2. When proceeding to the STOP mode, be sure to stop the peripheral hardware operation and execute the STOP instruction. 3. To decrease power dissipation in A/D converter, clear bit 7 (CS) of A/D converter mode register (ADM) to 0 and stop the A/D conversion operation before executing the HALT or STOP instruction.
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20.1.2 Standby function control register A wait time after the STOP mode is cleared upon interrupt request till the oscillation stabilizes is controlled with the oscillation stabilization time select register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H. Therefore, when the STOP mode is cleared with RESET input, the time till it is cleared is 218/fX.
Figure 20-1. Oscillation Stabilization Time Select Register Format
Symbol OSTS 7 0 6 0 5 0 4 0 3 0 2 1 0 Address FFFAH When Reset 04H R/W R/W
OSTS2 OSTS1 OSTS0
OSTS2 OSTS1 OSTS0 Oscillation Stabilization Time Selection 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 213/fX (819 s) 215/fX (3.28 ms) 216/fX (6.55 ms) 217/fX (13.1 ms) 218/fX (26.2 ms) Setting prohibited
Other than above
Caution
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The wait time after the STOP mode is cleared does not include the time from STOP mode clear to clock oscillation start (see "a" below), regardless of clearance by RESET input or by interrupt request generation.
STOP Mode Clear X1 Pin Voltage Waveform a VSS
Remarks
1. fX: Main system clock oscillation frequency 2. Values in parentheses apply to operation with fX = 10.0 MHz
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20.2 Standby Function Operations 20.2.1 HALT mode (1) HALT mode set and operating status The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the subsystem clock. The operating status in the HALT mode is described below.
Table 20-1. HALT Mode Operating Status
HALT Mode Setting Item When HALT instruction is executed during main system clock oscillation Without subsystem clockNote 1 Clock generator With subsystem clockNote 2 When HALT instruction is executed during subsystem clock oscillation When main system clock oscillation continues When main system clock oscillaton stops
Both main system clock and subsystem clock can be oscillated. Clock supply to the CPU stops.
CPU Port (output latch) 16-bit timer/event counter 8-bit timer/event counter
Operation stop. Status before HALT instruction execution is held. Operation enabled. Operation enabled. Operation stop. Operation enabled when TI1 and TI2 are selected for the count clock.
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Watchdog timer A/D converter Watch timer
Operation enabled. Operation enabled. Operation enabled when fX/2 is selected for the count clock.
8
Operation stop. Operation stop. Operation enabled. Operation enabled when fXT is selected for the count clock. Operation enabled when external SCK is selected.
Serial Interface
Other than auto- Operation enabled. matic transmit/ receive function Automatic transmit/receive function Operation stop.
External interrupt
INTP0
Operation enabled when the clock (fX/26 and fX/27) for the peripheral hardware are selected as sampling clock.
Operation stop.
INTP1 to INTP3 Operation enabled. Bus line in AD0 to AD7 External A8 to A15 High-impedance Status before HALT instruction execution is held. Low level High level High-impedance
Expansion ASTB WR, RD WAIT
Notes
1. 2.
Includes case when an external clock is not supplied in the subsystem clock. Includes case when an external clock is supplied in the subsystem clock.
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(2) HALT mode clear The HALT mode can be cleared with the following four types of sources. (a) Clear upon unmasked interrupt request The HALT mode is cleared when the unmasked interrupt request is generated. is executed. If interrupt request acknowledge is enabled, vectored interrupt service is carried out. If disabled, the next address instruction
Figure 20-2. HALT Mode Clear upon Interrupt Request Generation
Interrupt Request HALT Instruction
Wait
Standby Release Signal Operating Mode Operating Mode
HALT Mode
Wait Oscillation
Clock
Remarks 1. The broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged. 2. Wait time will be as follows:
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* When branched to the vector
: 16.5 to 17.5 clocks
* When not branched to the vector : 4.5 to 5.5 clocks (b) Clear upon non-maskable interrupt request The HALT mode is cleared and vectored interrupt service is carried out when the non-maskable interrupt request is generated whether interrupt request acknowledge is enabled or disabled. (c) Clear upon unmasked test input The HALT mode is cleared when the unmasked test signal inputs and the next address instruction of the HALT instruction is executed.
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(d) Clear upon RESET input The HALT mode is cleared when the RESET signal inputs. As is the case with normal reset operation, a program is executed after branch to the reset vector address.
Figure 20-3. HALT Mode Clear upon RESET Input
Wait (218/fX : 26.2 ms)
HALT Instruction
RESET Signal Operating Mode HALT Mode Oscillation Reset Period
Oscillation Stop
Oscillation Stabilization Wait Status Oscillation
Operating Mode
Clock
Remarks 1. fX: Main system clock oscillation frequency 2. Values in parentheses apply to operation with fX = 10.0 MHz
Table 20-2. Operation after HALT Mode Clear
Clear Source Maskable interrupt request MKxx 0 0
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PRxx 0 0 1 1 1 x -- -- -- --
IE 0 1 0 x 1 x x x x x
ISP x x 1 0 1 x x x x x
Operation Next address instruction execution Interrupt service execution Next address instruction execution
0 0 0 1 Non-maskable interrupt request Test input -- 0 1 RESET input --
Interrupt service execution HALT mode hold Interrupt service execution Next address instruction execution HALT mode hold Reset processing
Remark x: don't care
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20.2.2 STOP mode (1) STOP mode set and operating status The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock. Cautions 1. When the STOP mode is set, X1 input is internally short-circuited to VSS (ground potential) to suppress the leakage at the crystal oscillator. Thus, do not use the STOP mode in a system where an external clock is used for the main system clock. 2. Because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. Thus, the STOP mode is reset to the HALT mode immediately after execution of the STOP instruction. After the wait set using the oscillation stabilization time select register (OSTS), the operating mode is set. The operating status in the STOP mode is described below.
Table 20-3. STOP Mode Operating Status
STOP Mode Setting With subsystem clock Item Clock generator CPU Output port (output latch) 16-bit timer/event counter
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Without subsystem clock
Only main system clock stops oscillation. Operation stop. Status before STOP instruction execution is held. Operation stop. Operation enabled when TI1 and TI2 are selected for the count clock. Operation stop.
8-bit timer/event counter Watchdog timer A/D converter Watch timer
Operation enabled when fXT is selected for the count clock.
Operation stop.
Serial Interface
Other than auto- Operation enabled only when external input clock is selected as serial clock. matic transmit/ receive function Automatic transmit/receive function Operation stop.
External interrupt
INTP0
Operation disabled.
INTP1 to INTP3 Operation enabled. High-impedance Status before STOP instruction execution is held. Low level High level High-impedance
Bus line in AD0 to AD7 External A8 to A15
Expansion ASTB WR, RD WAIT
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(2) STOP mode clear The STOP mode can be cleared with the following three types of sources. (a) Clear upon unmasked interrupt request The STOP mode is cleared when the unmasked interrupt request is generated. If interrupt request acknowledge is enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out. If interrupt request acknowledge is disabled, the next address instruction is executed.
Figure 20-4. STOP Mode Clear upon Interrupt Request Generation
Interrupt Request STOP Instruction
Wait (Time set by OSTS)
Standby Release Signal Operating Mode Oscillation STOP Mode Oscillation Stop Oscillation Stabilization Wait Status Oscillation Operating Mode
Clock
Remark
The broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged.
(b) Clear upon unmasked test input
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The STOP mode is cleared when the unmasked test signal inputs. After the lapse of oscillation stabilization time, the instruction at the next address of the STOP instruction is executed.
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(c) Clear upon RESET input The STOP mode is cleared when the RESET signal inputs and after the lapse of oscillation stabilization time, reset operation is carried out.
Figure 20-5. STOP Mode Clear upon RESET Input
Wait (218/fX : 26.2 ms)
STOP Instruction
RESET Signal Operating Mode Oscillation STOP Mode Oscillation Stop Reset Period
Oscillation Stabilization Wait Status Oscillation
Operating Mode
Clock
Remarks
1. fX: Main system clock oscillation frequency 2. Values in parentheses apply to operation with fX = 10.0 MHz
Table 20-4. Operation after STOP Mode Clear
Clear Source Maskable interrupt request MKxx 0 0
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PRxx 0 0 1 1 1 x -- -- --
IE 0 1 0 x 1 x x x x
ISP x x 1 0 1 x x x x
Operation Next address instruction execution Interrupt service execution Next address instruction execution
0 0 0 1 Test input 0 1 RESET input --
Interrupt service execution STOP mode hold Next address instruction execution STOP mode hold Reset processing
Remark x: don't care
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RESET FUNCTION
CHAPTER 21
RESET FUNCTION
21.1 Reset Function The following two operations are available to generate the reset function. (1) External reset input with RESET pin (2) Internal reset by watchdog timer inadvertent program loop time detection External reset and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by RESET input. When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each hardware is set to the status as shown in Table 21-1. Each pin has high impedance during reset input or during oscillation stabilization time just after reset clear. When a high level is input to the RESET pin, the reset is cleared and program execution starts after the lapse of oscillation stabilization time (218/fX). The reset applied by watchdog timer overflow is automatically cleared after a reset and program execution starts after the lapse of oscillation stabilization time (218/fX) (see Figures 21-2 to 21-4). Cautions 1. For an external reset, input a low level for 10 ms or more to the RESET pin. 2. During reset input, main system clock oscillation remains stopped but subsystem clock oscillation continues. 3. When the STOP mode is cleared by reset, the STOP mode contents are held during reset input.
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However, the port pin becomes high-impedance.
Figure 21-1. Block Diagram of Reset Function
RESET
Reset Control Circuit
Reset Signal
Count Clock
Watchdog Timer Stop
Overflow
Interrupt Function
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Figure 21-2. Timing of Reset by RESET Input
X1 Normal Operation RESET Reset Period (Oscillation Stop) Oscillation Stabilization Time Wait Normal Operation (Reset Processing)
Internal Reset Signal Delay Port Pin
Delay
High-Impedance
Figure 21-3. Timing of Reset due to Watchdog Timer Overflow
X1 Normal Operation Watchdog Timer Overflow Reset Period (Oscillation Stop) Oscillation Stabilization Time Wait Normal Operation (Reset Processing)
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Internal Reset Signal
Port Pin
High-Impedance
Figure 21-4. Timing of Reset in STOP Mode by RESET Input
X1 Stop Instruction Execution Normal Operation RESET
Stop Status (Oscillation Stop)
Reset Period (Oscillation Stop)
Oscillation Stabilization Time Wait
Normal Operation (Reset Processing)
Internal Reset Signal Delay Port Pin
Delay
High-Impedance
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Table 21-1. Hardware Status after Reset (1/2)
Hardware Program counter (PC)
Note 1
Status after Reset The contents of reset vector tables (0000H and 0001H) are set.
Stack pointer (SP) Program status word (PSW) RAM Data memory General register Port (Output latch) Ports 0 to 3 (P0 to P3) Ports 4 to 6 (P4 to P6) Port mode register (PM0) (PM1, PM2, PM3, PM5, PM6) Pull-up resistor option register (PUO) Processor clock control register (PCC) Memory expansion mode register (MM) Internal memory size switching register (IMS) Oscillation stabilization time select register (OSTS) 16-bit timer/event counter Timer register (TM0) Compare register (CR00) Capture register (CR01) Clock select register (TCL0) Mode control register (TMC0)
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Undefined 02H UndefinedNote 2 UndefinedNote 2 00H Undefined 1FH FFH 00H 04H 10H Note 3 04H 0000H Undefined Undefined 00H 00H 00H 00H Undefined 00H 00H 00H
Output control register (TOC0) 8-bit timer/event counter Timer registers (TM1, TM2) Compare registers (CR10, CR20) Clock select register (TCL1) Mode control register (TMC1) Output control register (TOC1)
Notes
1. During reset input or oscillation stabilization time wait, only the PC contents among the hardware status become undefined. All other hardware status remain unchanged after reset. 2. When reset in the standby mode, pre-reset status is held even after reset. 3. The after-reset values of the memory size switching register (IMS) depend on products.
PD78011B, 78011BY: 42H, PD78012B, 78012BY: 44H, PD78013, 78013Y: C6H, PD78014, 78014Y, 78P014, 78P014Y: C8H
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Table 21-1. Hardware Status after Reset (2/2)
Hardware Watch timer Watchdog timer Serial interface Mode control register (TMC2) Clock select register (TCL2) Mode register (WDTM) Clock select register (TCL3) Shift registers (SIO0, SIO1) Mode registers (CSIM0, CSIM1) Serial bus interface control register (SBIC) Slave address register (SVA) Automatic data transmit/receive control register (ADTC) Automatic data transmit/receive address pointer (ADTP) Interrupt timing specify register (SINT) A/D converter Mode register (ADM) Conversion result register (ADCR) Input select register (ADIS) Interrupt Request flag registers (IF0L, IF0H) Mask flag registers (MK0L, MK0H) Priority specify flag registers (PR0L, PR0H) External interrupt mode register (INTM0) Key return mode register (KRM) Sampling clock select register (SCS)
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Status after Reset 00H 00H 00H 88H Undefined 00H 00H Undefined 00H 00H 00H 01H Undefined 00H 00H FFH FFH 00H 02H 00H
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CHAPTER 22
PD78P014, 78P014Y
The PD78P014 and 78P014Y are versions which incorporate a one-time programmable PROM or an EPROM enabled for program write, erase and rewrite. Table 22-1 lists differences between PD78P014, 78P014Y and mask ROM version.
Table 22-1. Differences between PD78P014, 78P014Y, and Mask ROM Version
Item Internal ROM configuration Internal ROM capacity
PD78P014, 78P014Y
One-time PROM/EPROM 32 Kbytes
Mask ROM Version Mask ROM
PD78011B, 78011BY: PD78012B, 78012BY: PD78013, 78013Y: PD78014, 78014Y:
8 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes 512 bytes 512 bytes 1024 bytes 1024 bytes
Internal high-speed RAM capacity
1024 bytes
PD78011B, 78011BY: PD78012B, 78012BY: PD78013, 78013Y: PD78014, 78014Y:
Internal ROM and internal high-speed RAM by memory size select register IC pin VPP pin P60 to P63 pin on-chip pull-up resistor
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Enable
Note
Disable
None Available None
Available None Available
internal mask option Electrical specification Refer to the data sheet for each part number.
Note
When RESET is input, the internal PROM capacity is set to 32 Kbytes, internal high-speed RAM capacity to 1024 bytes.
Caution
The noise resistance and noise radiation differs between PROM versions and mask ROM versions. If considering replacing PROM versions with mask ROM versions during the process from trial manufacturing to mass production, evaluate the CS versions (not ES versions) of mask ROM versions carefully.
22.1 Internal Memory Size Switching Register The PD78P014 and 78P014Y can select the internal memory capacity with the internal memory size switching register (IMS). The same memory mapping as that of the mask ROM version with a different internal memory capacity is possible by setting IMS. In order to make the memory maps of PD78P014 and 78P014Y identical to a mask ROM version, the value at the time the mask ROM version is reset must be set to IMS. For the mask ROM version, IMS does not need to be set. IMS is set with an 8-bit memory manipulation instruction. The value of IMS becomes the value shown in Table 22-2, at RESET. Caution To use a mask ROM version, do not set a value other than those shown in Table 22-2 to IMS.
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Figure 22-1. Internal Memory Size Switching Register Format
Symbol IMS 7 6 5 4 0 3 2 1 0 Address FFF0H When Reset Note R/W W
RAM2 RAM1 RAM0
ROM3 ROM2 ROM1 ROM0
ROM3 ROM2 ROM1 ROM0
Internal ROM Capacity Selection
0 0 0 0 1
0 0 1 1 0
0 1 0 1 0
1 0 0 0 0
4 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes Setting prohibited
Other than above
RAM2 RAM1 RAM0
Internal High-Speed RAM Capacity Selection
0 0 0 0 1 1 1
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0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
768 bytes 640 bytes 512 bytes 384 bytes 256 bytes Setting prohibited 1024 bytes 896 bytes
1
Note
The value of the memory size switching register at reset depends on the model (see Table 22-2).
Table 22-2. Internal Memory Size Switching Register Value at Reset
Part Number
Value at Reset 82H 64H 42H 44H
Part Number
Value at Reset C6H C8H
PD78001B, 78001BY PD78002B, 78002BY PD78011B, 78011BY PD78012B, 78012BY
PD78013, 78013Y PD78014, 78014Y PD78P014, 78P014Y
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22.2 PROM Programming The PD78P014 and 78P014Y incorporate a 32K-byte PROM as program memory. When programming the
PD78P014 and 78P014Y, the PROM programming mode is set by means of the VPP pin and the RESET pin. For
the connection of unused pins, see 1.5 or 2.5 Pin Configurations (Top View), (2) PROM programming mode. 22.2.1 Operating modes When +5 V or +12.5 V is applied to the VPP pin and a low-level signal is applied to the RESET pin, the PD78P014 and 78P014Y are set to the PROM programming mode. This is one of the operating modes shown in Table 22-3 below according to the setting of the CE and OE pins. The PROM contents can be read by setting the read mode.
Table 22-3. PROM Programming Operating Modes
Pin RESET Operating mode Program write Program verify Program inhibit Read Output disabled Standby +5 V +5 V L +12.5 V +6 V L H H L L H H L H L H x Data input Data output High-impedance Data output High-impedance High-impedance VPP VDD CE OE D0 to D7
Remark x: L or H
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22.2.2 PROM write procedure PROM contents can be written using the following procedure and high-speed writing is enabled. (1) Fix the RESET pin low, and supply +5 V to the VPP pin. Unused pins are handled as shown in 1.5 or 2.5 Pin Configuration, (Top View), (2) PROM programming mode. (2) Supply +6 V to the VDD pin and +12.5 V to the VPP pin. (3) Supply the initial address. (4) Supply the written data. (5) Supply the 1 ms program pulse (active low) to the CE pin. (6) Verify mode. If written, proceed to step (8). If not written, repeat steps (4) through (6). If you repeat 25 times and it can't be written, proceed to (7). (7) Stop the write operation as a defective device. (8) Supply write data and repeat times from (4) through (6) x 3 ms program pulse (additional write). (9) Increment the address. (10) Repeat steps (4) through (9) to the last address. The timing for steps (2) through (8) above is shown Figure 22-2.
Figure 22-2. PROM Write/Verify Timing
X-times Repeat
Write
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Verify
Additional Write
A0 to A14
Address Input
Hi-Z D0 to D7 Data Input
Hi-Z Data Output
Hi-Z Data Input
Hi-Z
+12.5 V VPP VDD +6 V VDD VDD 3Xms
CE (Input)
OE (Input)
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Figure 22-3. Write Procedure Flowchart
(1)
Start
(2)
Supply Power Voltage
(3)
Supply Initial Address
(4)
Supply Write Data
(5)
Supply Program Pulse
Write disabled (Less than 25 times)
(6) Write disabled (25th time) Verify Mode
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Write OK (8) Additional Write (3Xms pulse) X: Write repeat times
(9)
Increment Address
(10) Last Address Last Address
> Last Address End of Write
(7) Defective device
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22.2.3 PROM read procedure PROM contents can be read onto the external data bus (D0 to D7) using the following procedure. (1) Fix the RESET pin low, and supply +5 V to the VPP pin. Unused pins are handled as shown in 1.5 or 2.5 Pin Configurations (Top View), (2) PROM programming mode. (2) Supply +5 V to the VDD and VPP pins. (3) Input address of data to be read to pins A0 to A16. (4) Read mode. (5) Output data to pins D0 to D7. The timing for steps (2) to (5) above is shown in Figure 22 to 4.
Figure 22-4. PROM Read Timing
A0 to A14
Address Input
CE (Input)
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OE (Input)
D0 to D7
Hi-Z
Data Output
Hi-Z
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22.3 Erasure Characteristics (for PD78P014DW, 78P014YDW) Through exposure to light having a very short wavelength of less than 400 nm, contents of the programmed data can be erased (FFH). The PD78P014DW and 78P014YDW program memory contents are usually erased by ultraviolet rays having a wavelength of 254 nm. The amount of exposure needed to completely erase the PD78P014DW and 78P014YDW is at least 15 W x s/cm2 (ultraviolet ray strength x erasure time). The erasure time is about 15 to 20 minutes (when using a 12000 W/cm2 ultraviolet ray lamp). However, the required erasure time may be longer in some cases, such as when there has been deterioration of ultraviolet ray lamp performance or when the erasure window is dirty. When erasing, place the PD78P014DW and 78P014YDW within 2.5 cm of the ultraviolet ray lamp. If a filter has been attached to the ultraviolet ray lamp, remove the filter before erasing. 22.4 Opaque Film on Erasure Window (for PD78P014DW, 78P014YDW) When erasing EPROM contents, be sure to cover the erasure window with a shading film to prevent unintentional erasure of EPROM contents by light source other than the ultraviolet ray lamp and to prevent a light source from unintentionally affecting internal circuits other than the EPROM. 22.5 Screening of One-Time PROM Versions Because of their construction, one-time PROM versions (PD78P014CW, 78P014YCW, 78P014GC-AB8, 78P014YGCAB8) cannot be fully tested by NEC before shipment. After the necessary data has been written, it is recommended that screening is implemented in which PROM verification is performed after high-temperature storage under the following conditions.
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Storage Temperature 125C
Storage Time 24 hours
NEC is offering one-time PROM writing to marking, screening and verifying with charge under the name QTOPTM microcontroller. Please contact an NEC sales representative for the details.
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[MEMO]
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INSTRUCTION SET
CHAPTER 23
INSTRUCTION SET
The instruction sets for the PD78014 and 78014Y Subseries are described in the following pages. For the details of operations and mnemonics (instruction codes) of each instruction, refer to the 78K/0 Series User's Manual, Instructions (U12326E).
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23.1 Legend 23.1.1 Operand identifiers and description methods Operands are described in the "Operand" column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more description methods, select one of them. Alphabetic letters in capitals and symbols, #, !, $ and [ ] are key words and are described as they are. Each symbol has the following meaning. *# *! : Immediate data specification : Absolute address specification *$ : Relative address specification
* [ ] : Indirect address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to describe the #, !, $ and [ ] symbols. For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used for description.
Table 23-1. Operand Identifiers and Description Methods
Identifier r rp sfr sfrp saddr
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Description Method X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special function register symbolNote Special function register symbols (16-bit manipulatable register even addresses only)Note FE20H to FF1FH Immediate data or labels FE20H to FF1FH Immediate data or labels (even addresses only) 0000H to FFFFH Immediate data or labels (Only even addresses for 16-bit data transfer instructions)
saddrp addr16
addr11 addr5 word byte bit RBn
0800H to 0FFFH Immediate data or labels 0040H to 007FH Immediate data or labels (even addresses only) 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label RB0 to RB3
Note
FFD0H to FFDFH are not addressable.
Remark For special-function register symbols, refer to Table 5-5 Special Function Register List.
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23.1.2 Description of "operation" column A X B C D E H L AX BC DE HL PC SP PSW CY AC Z RBS IE NMIS (
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: A register; 8-bit accumulator : X register : B register : C register : D register : E register : H register : L register : AX register pair; 16-bit accumulator : BC register pair : DE register pair : HL register pair : Program counter : Stack pointer : Program status word : Carry flag : Auxiliary carry flag : Zero flag : Register bank select flag : Interrupt request enable flag : Non-maskable interrupt servicing flag : Memory contents indicated by address or register contents in parentheses : Higher 8 bits and lower 8 bits of 16-bit register : Logical product (AND) : Logical sum (OR) : Exclusive logical sum (exclusive OR) : Inverted data : 16-bit immediate data or label : Signed 8-bit data (displacement value) )
XH, XL addr16 jdisp8
23.1.3 Description of "flag operation" column (Blank) 0 1 x R : Unchanged : Cleared to 0 : Set to 1 : Set/cleared according to the result : Previously saved value is restored
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23.2 Operation List
Instruc- Mnemonic tion Group 8-bit data transfer MOV r, #byte saddr, #byte sfr, #byte A, r r, A A, saddr saddr, A A, sfr sfr, A A, !addr16 !addr16, A PSW, #byte A, PSW PSW, A A, [DE] [DE], A A, [HL] [HL], A A, [HL+byte]
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Note 3 Note 3
Operands
Byte Note 1 2 3 3 1 1 2 2 2 2 3 3 3 2 2 1 1 1 1 2 2 1 1 1 1 8 12 -- 4 4 8 8 -- -- 16 16 -- -- -- 8 8 8 8 16 16 12 12 12 12
Clock Note 2 -- 14 14 -- -- 10 10 10 10 18 + 2n 18 + 2m 14 10 10 10 + 2n 10 + 2m 10 + 2n 10 + 2m 18 + 2n 18 + 2m 14 + 2n 14 + 2m 14 + 2n 14 + 2m r byte
Operation Z
Flag AC CY
(saddr) byte sfr byte Ar rA A (saddr) (saddr) A A sfr sfr A A (addr16) (addr16) A PSW byte A PSW PSW A A (DE) (DE) A A (HL) (HL) A A (HL+byte) (HL+byte) A A (HL+B) (HL+B) A A (HL+C) (HL+C) A x x x x x x
[HL+byte], A A, [HL+B] [HL+B], A A, [HL+C] [HL+C], A
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed 3. Except r = A Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by processor clock control register (PCC). 2. Clock indicates when a program is in the internal ROM area. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written.
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Instruc- Mnemonic tion Group 8-bit data transfer XCH A, r
Operands
Byte Note 1
Note 3
Clock Note 2 -- 12 12 Ar
Operation Z
Flag AC CY
1 2 2 3 1 1 2 2 2 3 4 4 2 2 2 2
4 8 -- 16 8 8 16 16 16 12 16 -- 12 12 -- -- 8 8 20 20 8
A, saddr A, sfr A, !addr16 A, [DE] A, [HL] A, [HL+byte] A, [HL+B] A, [HL+C]
A (saddr) A sfr
20 + 2n + 2m A (addr16) 12 + 2n + 2m A (DE) 12 + 2n + 2m A (HL) 20 + 2n + 2m A (HL+byte) 20 + 2n + 2m A (HL+B) 20 + 2n + 2m A (HL+C) -- 20 20 16 16 16 16 -- -- 24 + 4n 24 + 4m -- rp word (saddrp) word sfrp word AX (saddrp) (saddrp) AX AX sfrp sfrp AX AX rp rp AX AX (addr16) (addr16) AX AX rp
16-bit data transfer
MOVW
rp, #word saddrp, #word sfrp, #word AX, saddrp saddrp, AX AX, sfrp sfrp, AX AX, rp rp, AX AX, !addr16 !addr16, AX
Note 4 Note 4
1 1 3 3
XCHW
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AX, rp
Note 4
1
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed 3. Except r = A 4. Only when rp = BC, DE or HL Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by processor clock control register (PCC). 2. Clock indicates when a program is in the internal ROM area. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written.
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Instruc- Mnemonic tion Group 8-bit Operation ADD
Operands
Byte Note 1
Clock Note 2 -- 16 -- -- 10 18 + 2n 10 + 2n 18 + 2n 18 + 2n 18 + 2n -- 16 -- -- 10 18 + 2n 10 + 2n 18 + 2n 18 + 2n 18 + 2n -- 16 -- -- 10 18 + 2n 10 + 2n 18 + 2n 18 + 2n 18 + 2n
Operation Z A, CY A+byte (saddr), CY (saddr)+byte A, CY A+r r, CY r+A A, CY A+(saddr) A, CY A+(addr16) A, CY A+(HL) A, CY A+(HL+byte) A, CY A+(HL+B) A, CY A+(HL+C) A, CY A+byte+CY (saddr), CY (saddr)+byte+CY A, CY A+r+CY r, CY r+A+CY A, CY A+(saddr)+CY A, CY A+(addr16)+CY A, CY A+(HL)+CY A, CY A+(HL+byte)+CY A, CY A+(HL+B)+CY A, CY A+(HL+C)+CY A, CY A-byte (saddr), CY (saddr)-byte A, CY A-r r, CY r-A A, CY A-(saddr) A, CY A-(addr16) A, CY A-(HL) A, CY A-(HL+byte) A, CY A-(HL+B) A, CY A-(HL+C) x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
Flag AC CY x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C]
Note 3
2 3 2 2 2 3 1 2 2 2 2 3
Note 3
8 12 8 8 8 16 8 16 16 16 8 12 8 8 8 16 8 16 16 16 8 12 8 8 8 16 8 16 16 16
ADDC
A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL+byte] A, [HL+B] A, [HL+C]
2 2 2 3 1 2 2 2 2 3
SUB
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A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL+byte] A, [HL+B] A, [HL+C]
Note 3
2 2 2 3 1 2 2 2
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed 3. Except r = A Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by processor clock control register (PCC). 2. Clock indicates when a program is in the internal ROM area. 3. n is the number of waits when the external memory expansion area is read.
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Instruc- Mnemonic tion Group 8-bit Operation SUBC
Operands
Byte Note 1
Clock Note 2 -- 16 -- -- 10 18 + 2n 10 + 2n 18 + 2n 18 + 2n 18 + 2n -- 16 -- -- 10 18 + 2n 10 + 2n 18 + 2n 18 + 2n 18 + 2n -- 16 -- -- 10 18 + 2n 10 + 2n 18 + 2n 18 + 2n 18 + 2n
Operation Z A, CY A-byte-CY (saddr), CY (saddr)-byte-CY A, CY A-r-CY r, CY r-A-CY A, CY A-(saddr)-CY A, CY A-(addr16)-CY A, CY A-(HL)-CY A, CY A-(HL+byte)-CY A, CY A-(HL+B)-CY A, CY A-(HL+C)-CY A Abyte (saddr) (saddr) byte A Ar r rA A A (saddr) A A (addr16) A A (HL) A A (HL+byte) A A (HL+B) A A (HL+C) A Abyte (saddr) (saddr) byte A Ar r rA A A (saddr) A A (addr16) A A (HL) A A (HL+byte) A A (HL+B) A A (HL+C) x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
Flag AC CY x x x x x x x x x x x x x x x x x x x x
A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL+byte] A, [HL+B] A, [HL+C]
Note 3
2 3 2 2 2 3 1 2 2 2 2 3
Note 3
8 12 8 8 8 16 8 16 16 16 8 12 8 8 8 16 8 16 16 16 8 12 8 8 8 16 8 16 16 16
AND
A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL+byte] A, [HL+B] A, [HL+C]
2 2 2 3 1 2 2 2 2 3
OR
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A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL+byte] A, [HL+B] A, [HL+C]
Note 3
2 2 2 3 1 2 2 2
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed 3. Except r = A Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by processor clock control register (PCC). 2. Clock indicates when a program is in the internal ROM area. 3. n is the number of waits when the external memory expansion area is read.
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Instruc- Mnemonic tion Group 8-bit Operation XOR
Operands
Byte Note 1
Clock Note 2 -- 16 -- -- 10 18 + 2n 10 + 2n 18 + 2n 18 + 2n 18 + 2n -- 16 -- -- 10 18 + 2n 10 + 2n 18 + 2n 18 + 2n 18 + 2n -- -- -- -- --
Operation Z A A byte (saddr) (saddr) byte AAr rrA A A (saddr) A A (addr16) A A (HL) A A (HL+byte) A A (HL+B) A A (HL+C) A-byte (saddr)-byte A-r r-A A-(saddr) A-(addr16) A-(HL) A-(HL+byte) A-(HL+B) A-(HL+C) AX, CY AX+word AX, CY AX-word AX-word AX A x X AX (Quotient), C (Remainder) AX/C x x x x x x x x x x x x x x x x x x x x x x x
Flag AC CY
A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL+byte] A, [HL+B] A, [HL+C]
Note 3
2 3 2 2 2 3 1 2 2 2 2 3
Note 3
8 12 8 8 8 16 8 16 16 16 8 12 8 8 8 16 8 16 16 16 12 12 12 32 50
CMP
A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL+byte] A, [HL+B] A, [HL+C]
x x x x x x x x x x x x x
x x x x x x x x x x x x x
2 2 2 3 1 2 2 2 3 3 3 2 2
16-bit
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ADDW SUBW CMPW
AX, #word AX, #word AX, #word X C
Operation
Multiply/ MULU Divide DIVUW
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed 3. Except r = A Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by processor clock control register (PCC). 2. Clock indicates when a program is in the internal ROM area. 3. n is the number of waits when the external memory expansion area is read.
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Instruc- Mnemonic tion Group Increase/ INC Decrease DEC r
Operands
Byte Note 1 1 2 1 2 1 1 1 1 1 1 2 4 8 4 8 8 8 4 4 4 4 20
Clock Note 2 -- 12 -- 12 -- -- -- -- -- -- 24 + 2n + 2m r r+1
Operation Z x x x x
Flag AC CY x x x x
saddr r saddr INCW DECW rp rp A, 1 A, 1 A, 1 A, 1 [HL]
(saddr) (saddr)+1 r r-1 (saddr) (saddr)-1 rp rp+1 rp rp-1 (CY, A7 A0, Am-1 Am) x 1 (CY, A0 A7, Am+1 Am) x 1 (CY A0, A7 CY, Am-1 Am) x 1 (CY A7, A0 CY, Am+1 Am) x 1 A3-0 (HL)3-0, (HL)7-4 A3-0, (HL)3-0 (HL)7-4 A3-0 (HL)7-4, (HL)3-0 A3-0, (HL)7-4 (HL)3-0 Decimal Adjust Accumulator after Addition
Rotation
ROR ROL RORC ROLC ROR4
x x x x
ROL4
[HL]
2
20
24 + 2n + 2m
BCD Adjust
ADJBA
2
8
--
x x
x x
x x x x x x x
ADJBS
2
8
--
Decimal Adjust Accumulator after Subtract CY (saddr.bit) CY sfr.bit CY A.bit CY PSW.bit CY (HL).bit (saddr.bit) CY sfr.bit CY A.bit CY PSW.bit CY (HL).bit CY
Bit Manipulation
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MOV1
CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit saddr.bit, CY sfr.bit, CY A.bit, CY PSW.bit, CY [HL].bit, CY
3 3 2 3 2 3 3 2 3 2
12 -- 8 -- 12 12 -- 8 -- 12
14 14 -- 14 14 + 2n 16 16 -- 16 16 + 2n + 2m
x
x
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by processor clock control register (PCC). 2. Clock indicates when a program is in the internal ROM area. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written.
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INSTRUCTION SET
Instruc- Mnemonic tion Group Bit Manipulation AND1
Operands
Byte Note 1
Clock Note 2 14 14 -- 14 14 + 2n 14 14 -- 14 14 + 2n 14 14 -- 14 14 + 2n 12 16 -- 12 16 + 2n + 2m 12 16 -- 12 16 + 2n + 2m -- -- --
Operation
Flag Z AC CY
CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit
3 3 2 3 2 3 3 2 3 2 3 3 2 3 2 2 3 2 2 2 2 3 2 2 2 1 1 1
12 -- 8 -- 12 12 -- 8 -- 12 12 -- 8 -- 12 8 -- 8 -- 12 8 -- 8 -- 12 4 4 4
CY CY (saddr.bit) CY CY sfr.bit CY CY A.bit CY CY PSW.bit CY CY (HL).bit CY CY (saddr.bit) CY CY sfr.bit CY CY A.bit CY CY PSW.bit CY CY (HL).bit CY CY (saddr.bit) CY CY sfr.bit CY CY A.bit CY CY PSW.bit CY CY (HL).bit (saddr.bit) 1 sfr.bit 1 A.bit 1 PSW.bit 1 (HL).bit 1 (saddr.bit) 0 sfr.bit 0 A.bit 0 PSW.bit 0 (HL).bit 0 CY 1 CY 0 CY CY x x x x
x x x x x x x x x x x x x x x
OR1
CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit
XOR1
CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit
SET1
saddr.bit sfr.bit A.bit PSW.bit [HL].bit
x
CLR1
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saddr.bit sfr.bit A.bit PSW.bit [HL].bit
x 1 0 x
SET1 CLR1 NOT1
CY CY CY
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by processor clock control register (PCC). 2. Clock indicates when a program is in the internal ROM area. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written.
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INSTRUCTION SET
Instruc- Mnemonic tion Group Call Return CALLF CALL
Operands
Byte Note 1
Clock Note 2 --
Operation Z (SP-1) (PC+3)H, (SP-2) (PC+3)L, PC addr16, SP SP-2 (SP-1) (PC+2)H, (SP-2) (PC+2)L, PC15-11 00001, PC10-0 addr11, SP SP-2
Flag AC CY
!addr16
3
14
!addr11
2
10
--
CALLT
[addr5]
1
12
--
(SP-1) (PC+1)H, (SP-2) (PC+1)L, PCH (00000000, addr5+1), PCL (00000000, addr5), SP SP-2
BRK
1
12
--
(SP-1) PSW, (SP-2) (PC+1)H, (SP-3) (PC+1)L, PCH (003FH), PCL (003EH), SP SP-3, IE 0
RET
1
12
--
PCH (SP+1), PCL (SP), SP SP+2 PCH (SP+1), PCL (SP), PSW (SP+2), SP SP+3, NMIS 0 R R R
RETI
1
12
--
RETB
1
12
--
PCH (SP+1), PCL (SP), PSW (SP+2), SP SP+3 (SP-1) PSW, SP SP-1 (SP-1) rpH, (SP-2) rpL, SP SP-2 PSW (SP), SP SP+1 rpH (SP+1), rpL (SP), SP SP+2 SP word SP AX AX SP
R
R
R
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PUSH
PSW rp
1 1
4 8
-- --
lation POP PSW rp 1 1 4 8 -- --
R
R
R
MOVW
SP, #word SP, AX AX, SP
4 2 2
-- -- --
20 16 16
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by processor clock control register (PCC). 2. Clock indicates when a program is in the internal ROM area.
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INSTRUCTION SET
Instruc- Mnemonic tion Group Uncon- BR ditional Branch Conditional BC BNC
Operands
Byte Note 1
Clock Note 2 -- -- -- -- -- -- -- 18
Operation Z PC addr16 PC PC + 2 + jdisp8 PCH A, PCL X PC PC + 2 + jdisp8 if CY = 1 PC PC + 2 + jdisp8 if CY = 0 PC PC + 2 + jdisp8 if Z = 1 PC PC + 2 + jdisp8 if Z = 0 PC PC + 3 + jdisp8 if (saddr.bit) = 1 PC PC + 4 + jdisp8 if sfr.bit = 1 PC PC + 3 + jdisp8 if A.bit = 1 PC PC + 3 + jdisp8 if PSW.bit = 1 PC PC + 3 + jdisp8 if (HL).bit = 1 PC PC + 4 + jdisp8 if (saddr.bit) = 0 PC PC + 4 + jdisp8 if sfr.bit = 0 PC PC + 3 + jdisp8 if A.bit = 0 PC PC + 4 + jdisp8 if PSW.bit = 0 PC PC + 3 + jdisp8 if (HL).bit = 0 PC PC + 4 + jdisp8 if (saddr.bit) = 1 then reset (saddr.bit)
Flag AC CY
!addr16 $addr16 AX $addr16 $addr16 $addr16 $addr16 saddr.bit, $addr16
3 2 2 2 2 2 2 3
12 12 16 12 12 12 12 16
Branch BZ BNZ BT
sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 BF saddr.bit, $addr16
4 3 3 3 4
-- 16 -- 20 20
22 -- 18 22 + 2n 22
sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 BTCLR
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4 3 4 3 4
-- 16 -- 20 20
22 -- 22 22 + 2n 24
saddr.bit, $addr16
sfr.bit, $addr16
4
--
24
PC PC + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit PC PC + 3 + jdisp8 if A.bit = 1 then reset A.bit PC PC+4 + jdisp8 if PSW.bit = 1 x then reset PSW.bit PC PC + 3 + jdisp8 if (HL).bit = 1 then reset (HL).bit x x
A.bit, $addr16
3
16
--
PSW.bit, $addr16
4
--
24
[HL].bit, $addr16
3
20
24 + 2n +2m
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by processor clock control register (PCC). 2. Clock indicates when a program is in the internal ROM area. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written.
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INSTRUCTION SET
Instruc- Mnemonic tion Group Conditional Branch DBNZ
Operands
Byte Note 1
Clock Note 2 --
Operation Z B B-1, then PC PC + 2 + jdisp8 if B 0 C C-1, then PC PC + 2 + jdisp8 if C 0 (saddr) (saddr) - 1, then PC PC + 3 + jdisp8 if (saddr) 0 RBS1, 0 n No Operation IE 1 (Enable Interrupt) IE 0 (Disable Interrupt) Set HALT Mode Set STOP Mode
Flag AC CY
B, $addr16
2
12
C, $addr16
2
12
--
saddr, $addr16
3
16
20
CPU Control
SEL NOP EI DI HALT STOP
RBn
2 1 2 2 2 2
8 4 -- -- 12 12
-- -- 12 12 -- --
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by processor clock control register (PCC). 2. Clock indicates when a program is in the internal ROM area.
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INSTRUCTION SET
23.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
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CHAPTER 23
INSTRUCTION SET
Second Operand First Operand A
#byte
A
rNote
sfr
saddr
!addr16
PSW
[DE]
[HL]
[HL+byte] $addr16 [HL+B] [HL+C]
1
None
ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV
MOV XCH
MOV XCH ADD
MOV XCH ADD
ROR ROL RORC ROLC
ADDC ADDC SUB SUB
SUBC SUBC AND OR XOR CMP AND OR XOR CMP INC DEC
r
MOV
MOV ADD ADDC SUB SUBC AND OR XOR CMP
B, C
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DBNZ MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV DBNZ INC DEC
sfr saddr
!addr16 PSW MOV
MOV MOV PUSH POP
[DE] [HL]
MOV MOV ROR4 ROL4
[HL+byte] [HL+B] [HL+C] X C
MOV
MULU DIVUW
Note
Except r = A
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CHAPTER 23
INSTRUCTION SET
(2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second Operand First Operand AX ADDW SUBW CMPW rp MOVW MOVWNote INCW DECW PUSH POP sfrp saddrp !addr16 SP MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW XCHW MOVW MOVW MOVW MOVW #word AX rpNote sfrp saddrp !addr16 SP None
Note
Only when rp = BC, DE, HL
(3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
Second Operand First Operand
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A.bit
sfr.bit
saddr.bit
PSW.bit
[HL].bit
CY
$addr16
None
A.bit
MOV1
BT BF BTCLR
SET1 CLR1
sfr.bit
MOV1
BT BF BTCLR
SET1 CLR1
saddr.bit
MOV1
BT BF BTCLR
SET1 CLR1
PSW.bit
MOV1
BT BF BTCLR
SET1 CLR1
[HL].bit
MOV1
BT BF BTCLR
SET1 CLR1
CY
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
SET1 CLR1 NOT1
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INSTRUCTION SET
(4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
Second Operand First Operand Basic instruction BR CALL BR CALLF CALLT BR BC BNC BZ BNZ Compound instruction BT BF BTCLR DBNZ AX !addr16 !addr11 [addr5] $addr16
(5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
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CHAPTER 23
INSTRUCTION SET
[MEMO]
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APPENDIX A
DIFFERENCES BETWEEN PD78014, 78014H, AND 78018F SUBSERIES
APPENDIX A DIFFERENCES BETWEEN PD78014, 78014H, AND 78018F SUBSERIES
Table A-1 shows the major differences between the PD78014, 78014H, and 78018F Subseries.
Table A-1. Major Differences between PD78014, 78014H, and 78018F Subseries (1/2)
Part Number Item EMI noise measure Y Subseries PROM version Supply voltage Internal high-speed RAM size
PD78014 Subseries
None Provided
PD78014H Subseries
Provided None
PD78018F Subseries
None Provided
PD78P014
VDD = 2.7 to 6.0 V
PD78P018F
VDD = 1.8 to 5.5 V
PD78011B: 512 bytes PD78012B: 512 bytes PD78013: 1024 bytes PD78014: 1024 bytes PD78P014: 1024 bytes
PD78011H: PD78012H: PD78013H: PD78014H:
512 bytes 512 bytes 1024 bytes 1024 bytes
PD78011F: 512 bytes PD78012F: 512 bytes PD78013F: 1024 bytes PD78014F: 1024 bytes PD78015F: 1024 bytes PD78016F: 1024 bytes PD78018F: 1024 bytes PD78P018F: 1024 bytes PD78011F: None PD78012F: None PD78013F: None PD78014F: None PD78015F: 512 bytes PD78016F: 512 bytes PD78018F: 1024 bytes PD78P018F: 1024 bytes
Internal expansion RAM size
None
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Operation mode of serial interface (Y Subseries)
3-wire/2-wire/SBI/I2C: 1 ch 3-wire (with automatic transmission/reception): 1 ch
--
3-wire/2-wire/I2C: 1 ch 3-wire (with automatic transmission/reception): 1 ch
Bit 5 (SIC) of interrupt timing When SIC = 1: sets CSIIF0 specification register (SINT) in (interrupt request flag) on SBI mode (selection of INTCSI0 detection of bus release interrupt source) Bit 5 (SIC) of interrupt timing specification register (SINT) in I2C bus mode (selection of INTCSI0 interrupt source) When SIC = 1: Sets CSIIF0 (interrupt request flag) on detection of stop condition
When SIC = 1: Sets CSIIF0 (interrupt request flag) on detection of bus release and at end of transfer
--
When SIC = 1: Sets CSIIF0 (interrupt request flag) on detection of stop condition and at end of transfer
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APPENDIX A
DIFFERENCES BETWEEN PD78014, 78014H, AND 78018F SUBSERIES
Table A-1. Major Differences between PD78014, 78014H, and 78018F Subseries (2/2)
Part Number Item Function of bit 7 (BSYE) of serial bus interface control register (SBIC) (Y Subseries)
PD78014 Subseries
Control of synchronous bus signal output * When BSYE = 0 Disables output of busy signal in synchronization with falling edge of clock of SCK0 immediately after instruction that clears this bit to 0 in SBI mode. Make sure that BSYE = 0 in I2C bus mode. * When BSYE = 1 Outputs busy signal from falling edge of SCK0 following acknowledge signal in SBI mode. None
PD78014H Subseries
--
PD78018F Subseries
Control of N-ch open-drain output for transmission in I2C bus mode * When BSYE = 0 Enables output (transmission) * When BSYE = 1 Disables output (reception)
Automatic data transmission/ reception interval specification register (ADTI) Package
Provided
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* 64-pin plastic shrink DIP (750 mil) * 64-pin ceramic shrink DIP (w/window) (750 mil)Note * 64-pin plastic QFP (14 x 14 mm)
* 64-pin plastic shrink DIP (750 mil) * 64-pin plastic QFP (14 x 14 mm) * 64-pin plastic LQFP (12 x 12 mm)
* 64-pin plastic shrink DIP (750 mil) * 64-pin ceramic shrink DIP (w/window) (750 mil)Note * 64-pin plastic QFP (14 x 14 mm) * 64-pin plastic LQFP (12 x 12 mm) * 64-pin ceramic WQFN (14 x 14 mm)Note
Programmer adapter
PA-78P014CW PA-78P014GC
PA-78P018CW PA-78P018GC PA-78P018GK PA-78P018KK-S IE-78014-R-EM-A
Emulation board
IE-78014-R-EM or IE-78014-R-EM-A
Access timing to external memory
Differs between PD78014 Subseries and other subseries. Refer to individual data sheet
Electrical characteristics, recom- Refer to individual data sheet. mended soldering conditions
Note
PROM version only
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APPENDIX B
DEVELOPMENT TOOLS
APPENDIX B
DEVELOPMENT TOOLS
The following development tools are available for the development of systems which employ the PD78014 and 78014Y Subseries. Figure B-1 shows the development tools configuration.
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APPENDIX B
DEVELOPMENT TOOLS
Figure B-1. Development Tools Configuration
Embedded software
PROM programmer control software
* Real-time OS, OS * Fuzzy inference development support system
* PG-1500 controller
Language processing software * * * * * Assembler package C compiler package C library source file System simulator Screen debugger or Integrated debugger * Device file
Host machine (PC or EWS)
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Interface adapter (Only for integrated debugger)
PROM programming environment PROM programmer
In-circuit emulator Interface adapter (Only for integrated debugger) Emulation board
Programmer adapter
PROM version
Emulation probe
Conversion socket or Conversion adapter Target system
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APPENDIX B
DEVELOPMENT TOOLS
B.1 Language Processing Software
RA78K/0 Assembler Package This is a program to convert a program written in mnemonics into an object code executable with a microcontroller. Further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization. Use RA78K/0 assembler package in combination with DF78014 device file (option). Part Number: SxxxxRA78K0 CC78K/0 C Compiler Package This is a program to convert a program written in C language into an object code executable with a microcontroller. Use CC78K/0 C compiler package in combination with RA78K/0 assembler package and DF78014 device file (option). Part Number: SxxxxCC78K0 DF78014Note Device file This file contains device-specific information. Use DF78014 device file in combination with RA78K/0, CC78K/0, SM78K0, ID78K0, and SD78K/0 (option). Part Number: SxxxxDF78014 CC78K/0-L C Library Source File A function source program configurating object library included in CC78K/0 C compiler package. This is needed when modifying the object library included in the C compiler package to customer's specification. Part Number: SxxxxCC78K0-L
Note
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DF78014 can be used in common with any of the RA78K/0, CC78K/0, SM78K0, ID78K0, and SD78K/0 products.
Remark xxxx of the part number differs depending on the host machine or OS used. Refer to the table below.
SxxxxRA78K0 SxxxxCC78K0 SxxxxDF78014 SxxxxCC78K0-L
xxxx 5A13 5A10
Host Machine PC-9800 series
Operating System MS-DOS Ver.3.30 to Ver.6.2Note
Supply Medium 3.5-inch 2HD 5-inch 2HD
7B13 7B10 3H15 3P16 3K15 3M15
IBM PC/AT and compatible machine HP9000 series 300TM HP9000 series 700TM SPARCstationTM EWS4800 series (RISC)
See B.4
3.5-inch 2HC 5-inch 2HC
HP-UXTM(Rel7.05B) HP-UX(Rel9.01) SunOSTM(Rel4.1.1) EWS-UX/V(Rel4.0)
Cartridge tape (QIC-24) Digital audio tape (DAT) Cartridge tape (QIC-24)
Note
MS-DOS Ver. 5.0 or later have a task swap function, but this task swap function is not used in above software.
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APPENDIX B
DEVELOPMENT TOOLS
B.2 PROM Programming Tools B.2.1 Hardware
PG-1500 PROM programmer This is a PROM programmer capable of programming the single-chip microcontroller's on-chip PROM by manipulating from the stand-alone or host machine through connection of a programmer adapter separately purchasable and the supplied board. It can also program typical PROMs the capacities of which range from 256 Kbits to 4 Mbits. PA-78P014CW PA-78P014GC PROM programmer adapter This PROM programmer adapter is for the PD78P014 and 78P014Y and is connected to the PG-1500. PA-78P014CW: 64-pin plastic shrink DIP (CW type) PA-78P014GC: 64-pin plastic QFP (GC-AB8 type)
B.2.2 Software
PG-1500 Controller The PG-1500 is controlled from the host machine through connection with the host machine and PG-1500 via serial and/or parallel interface(s). Part number: SxxxxPG1500
Remark Part number xxxx changes by the host machine or OS to be used.
SxxxxPG1500
xxxx 5A13 5A10
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Host Machine PC-9800 series
Operating System MS-DOS Ver.3.30 to Ver.6.2Note
Supply Medium 3.5-inch 2HD 5-inch 2HD
7B13 7B10
IBM PC/AT and compatible machine
See B.4
3.5-inch 2HD 5-inch 2HC
Note MS-DOS Ver. 5.0 or later have a task swap function, but this task swap function cannot be used in the above software.
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APPENDIX B
DEVELOPMENT TOOLS
B.3 Debugging Tools B.3.1 Hardware
IE-78000-R-A In-circuit emulator (For integrated debugger)
This is the in-circuit emulator for debugging hardware and/or software when a system is developed with 78K/0 Series devices. This emulator is designed to be used with the integrated debugger (ID78K0). This is used together with interface adapter to connect an emulation probe or host machine.
IE-70000-98-IF-B Interface adapter IE-70000-98N-IF Interface adapter IE-70000-PC-IF-B Interface adapter IE-78000-R-SV3 Interface adapter
This adapter is needed when PC-9800 (excluding notebook models) is used as a host machine of IE-78000-R-A. This adapter and cable are needed when a PC-9800 notebook-type personal computer is used as a host machine of IE-78000-R-A. This adapter is needed when IBM PC/AT is used as a host machine of IE-78000-R-A.
This adapter and cable are needed when an EWS is used as a host machine of IE78000-R-A. This adaptor should be connected to the internal board of IE-78000-R-A. 10Base-5 is supported for EthernetTM connection. It needs a commercially available adapter for other connection.
IE-78000-R In-circuit emulator (For screen debugger)
This is the in-circuit emulator for debugging hardware and/or software when a system is developed with 78K/0 Series devices. This emulator is designed to be used with the screen debugger (SD78K/0). This is used together with emulation probe. This emulator provides an efficient debugging environment by connecting it with a host computer and a PROM programmer.
IE-78014-R-EM
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This is the board which emulates the peripheral hardware operations specific for the device (For 5 V). This is used together with in-circuit emulator. This is the board which emulates hardware operations specific for the device (For 3 to 5.5 V). This is used together with in-circuit emulator. This is the probe to connect the in-circuit emulator with a target system. This is for 64-pin plastic shrink DIP (CW type). This is the probe to connect the in-circuit emulator with a target system. This is for 64-pin plastic QFP (GC-AB8 type). One 64-pin socket EV-9200GC-64 is included to facilitate development of target system.
Emulation board IE-78014-R-EM-A Emulation board EP-78240CW-R Emulation probe EP-78240GC-R Emulation probe
EV-9200GC-64 Conversion socket
This socket connects EP-78240GC-R to a target system board designed for 64-pin plastic QFP (GC-AB8 type).
Remark The EV-9200GC-64 is sold in five units as a set.
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APPENDIX B
DEVELOPMENT TOOLS
B.3.2 Software (1/3)
SM78K0 System simulator It is possible to debug at C source level or assembler level while simulating target system on the host machine. SM78K0 runs on Windows. By using SM78K0, logic and performance verification of application without in-circuit emulator is possible independently of hardware development, and development efficiency and software quality will thus be improved. This is used together with the separately sold device file (DF78014). Part Number: SxxxxSM78K0
Remark Part number xxxx changes by the host machine or OS to be used.
SxxxxSM78K0
xxxx AA13
Host Machine PC-9800 series
Operating System MS-DOS Ver.3.30 to Ver.6.2Note + Windows Ver. 3.0 to Ver. 3.1
Supply Medium 3.5-inch 2HD
AB13
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IBM PC/AT and compatible machine (Japanese Windows)
Refer to B.4
3.5-inch 2HC
BB13
IBM PC/AT and compatible machine (English Windows)
Note
MS-DOS Ver. 5.0 or later have a task swap function, but this task swap function cannot be used in the above software.
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APPENDIX B
DEVELOPMENT TOOLS
B.3.2 Software (2/3)
ID78K0 Integrated debugger This debugger is a control program used to debug applications of the 78K/0 Series devices. This software has a Windows-based (PC version) or OSF/MotifTM-based (EWS version) graphical user interface to provide comfortable operation environments. It also has an enhanced debugging function for C language support, and it is possible to display trace results at the C-language level by using its window integration feature which links source programs, disassembled display, and memory content display to their trace results. In addition, the efficiency when a program is debugged on a real-time operating system can be improved by incorporating function extension modules such as task debugger and system performance analyzer. This is used together with the separately sold device file (DF78014) Part Number: SxxxxID78K0
Remark Part number xxxx changes by the host machine or OS to be used.
SxxxxID78K0
xxxx AA13
Host Machine PC-9800 series
Operating System MS-DOS Ver.3.30 to Ver.6.2Note + Windows (Ver. 3.1)
Supply Medium 3.5-inch 2HD
AB13
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IBM PC/AT and compatible machine (Japanese Windows)
See B.4
3.5-inch 2HC
BB13
IBM PC/AT and compatible machine (English Windows)
3P16 3K15 3K13 3R16 3R13 3M15
HP9000 series 700 SPARCstation
HP-UX(Rel9.0.1) SunOS(Rel4.1.1)
Digital audio tape (DAT) Cartridge tape (QIC-24) 3.5-inch 2HC
NEWSTM (RISC)
NEWS-OSTM(6.1x)
1/4-inch CGMT 3.5-inch 2HC
EWS4800 series (RISC)
EWS-UX/V(Rel4.0)
Cartridge tape (QIC-24)
Note
MS-DOS Ver. 5.0 or later have a task swap function, but this task swap function cannot be used in the above software.
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APPENDIX B
DEVELOPMENT TOOLS
B.3.2 Software (3/3)
SD78K/0 Screen debugger The IE-78000-R is controlled in the host machine through connection with the host machine and IE-78000-R via serial interface (RS-232-C). This is used together with the separately sold device file (DF78014). Part Number: SxxxxSD78K0 DF78014
Note
This file has device-specific information. This is used together with the separately sold device file (RA78K/0, CC78K/0, SM78K0, ID78K0, SD78K/0) Part Number: SxxxxDF78014
Device file
Note
DF78014 can be used in RA78K/0, CC78K/0, SM78K0, and SD78K/0 all in common.
Remark Part number xxxx changes by the host machine or OS to be used.
SxxxxSD78K0 SxxxxDF78014
xxxx 5A13 5A10
Host Machine PC-9800 series
Operating System MS-DOS Ver.3.30 to Ver.6.2Note
Supply Medium 3.5-inch 2HD 5-inch 2HD
7B13 7B10
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IBM PC/AT and compatible machine
Refer to B.4
3.5-inch 2HC 5-inch 2HC
Note
MS-DOS Ver. 5.0 or later have a task swap function, but this task swap function cannot be used in the above software.
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APPENDIX B
DEVELOPMENT TOOLS
B.4 OS for IBM PC The following OSs for IBM PC are supported. When operating SM78K0, ID78K0, FE9200 (See C.2 Fuzzy Inference Development Support System), Windows (Ver. 3.0 to Ver. 3.1) is necessary.
OS PC DOS Version Ver. 5.02 to Ver. 6.3 J6.1/VNote to J6.3/VNote IBM DOSTM MS-DOS J5.02/VNote Ver. 5.0 to Ver. 6.22 5.0/VNote to 6.2/VNote
Note
Only English mode is supported.
Caution MS-DOS Ver. 5.0 or later have a task swap function, but this task swap function cannot be used in this software.
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APPENDIX B
DEVELOPMENT TOOLS
B.5 System-up Method from Other In-Circuit Emulator to In-Circuit Emulator for the 78K/0 Series When you already have an in-circuit emulator for the 78K Series or the 75X/XL Series, you can use that in-circuit emulator as the equivalent of a 78K/0 Series in-circuit emulator IE-78000-R or IE-78000-R-A by replacing the internal break board with the IE-78000-R-BK.
Table B-1. System-up Method from Other In-Circuit Emulator to IE-78000-R
Series Name 75X/XL Series 78K/I Series 78K/II Series In-circuit Emulator Owned IE-75000-R
Note
Board to be Purchased IE-78000-R-BK
, IE-75001-R
IE-78130-R, IE-78140-R IE-78230-RNote, IE-78230-R-A IE-78240-RNote, IE-78240-R-A
78K/III Series
IE-78320-RNote, IE-78327-R IE-78330-R, IE-78350-R
Note
Available for maintenance purposes only.
Table B-2. System-up Method from Other In-Circuit Emulator to IE-78000-R-A
Series Name 75X/XL Series 78K/I Series
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In-circuit Emulator Owned IE-75000-RNote 1, IE-75001-R IE-78130-R, IE-78140-R IE-78230-RNote 1, IE-78230-R-A, IE-78240-RNote 1, IE-78240-R-A
Board to be Purchased IE-78000-R-BKNote 2
78K/II Series
78K/III Series
IE-78320-RNote 1, IE-78327-R, IE-78330-R, IE-78350-R
78K/0 Series
IE-78000-R
--Note 2
Notes 1. Available for maintenance purposes only. 2. It is needed to take out to NEC to change a part of in-circuit emulator and replace the control/trace board with the supervisor board
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APPENDIX B
DEVELOPMENT TOOLS
Package Drawing and Footprint of Conversion Socket (EV-9200GC-64)
Figure B-2. EV-9200GC-64 Package Drawing (for reference only)
A E B F M R N O Q S D C T K EV-9200GC-64-G0
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EV-9200GC-64
1 No.1 pin index P
G H I ITEM A B C D E F G H I J K L M N O P Q R S T MILLIMETERS 18.8 14.1 14.1 18.8 4-C 3.0 0.8 6.0 15.8 18.5 6.0 15.8 18.5 8.0 7.8 2.5 2.0 1.35 0.35 0.1 INCHES 0.74 0.555 0.555 0.74 4-C 0.118 0.031 0.236 0.622 0.728 0.236 0.622 0.728 0.315 0.307 0.098 0.079 0.053 0.014 +0.004 -0.005
2.3 1.5
J
0.091 0.059
L
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APPENDIX B
DEVELOPMENT TOOLS
Figure B-3. EV-9200GC-64 Footprint (for reference only)
G
J K
D
E
F
L
C B A EV-9200GC-64-P1 ITEM A B C D E
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MILLIMETERS 19.5 14.8 0.8 0.02 x 15=12.0 0.05
INCHES 0.768 0.583 0.031+0.002 x -0.001 0.591=0.472 +0.003 -0.002
0.8 0.02 x 15=12.0 0.05 0.031+0.002 x 0.591=0.472 +0.003 -0.001 -0.002 14.8 19.5 6.00 0.08 6.00 0.08 0.5 0.02 0.583 0.768 0.236 +0.004 -0.003 0.236 +0.004 -0.003 0.197 +0.001 -0.002
F G H I J K L Caution
2.36 0.03 2.2 0.1 1.57 0.03
0.093 +0.001 -0.002 0.087 +0.004 -0.005 0.062 +0.001 -0.002
Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E).
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I
H
APPENDIX C EMBEDDED SOFTWARE
APPENDIX C
EMBEDDED SOFTWARE
The following embedded software are available for efficient program development and maintenance of the
PD78014 and 78014Y Subseries.
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APPENDIX C
EMBEDDED SOFTWARE
C.1 Real-time OS (1/2)
RX78K/0 Real-time OS Real-time OS which is based on the ITRON specification. Supplied with the RX78K/0 nucleus and a tool to prepare multiple information tables (configurator). Used in combination with RA78K/0 assembler package (option) and device file (DF78014) (option). Part Number: SxxxxRX78013-
Caution When purchasing the RX78K/0, fill in the purchase application form in advance, and sign the User Agreement. Remark xxxx and of the part number differs depending on host machine and OS, etc.
SxxxxRX78013-
001 100K 001M 010M S01 xxxx 5A13 5A10
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Product Outline Evaluation object Mass production object
Maximum number for use in mass production Do not use for mass-producing product. 100,000 1,000,000 10,000,000
Source program
Source program of mass production object
Host Machine PC-9800 series
Operating System MS-DOS Ver.3.30 to Ver.6.2Note
Supply Medium 3.5-inch 2HD 5-inch 2HD
7B13 7B10 3H15 3P16 3K15 3M15
IBM PC/AT and compatible machine HP9000 series 300 HP9000 series 700 SPARCstation EWS4800 series (RISC)
See B.4
3.5-inch 2HC 5-inch 2HC
HP-UX(Rel7.05B) HP-UX(Rel9.01) SunOS(Rel4.1.1) EWS-UX/V(Rel4.0)
Cartridge tape (QIC-24) Digital audio tape (DAT) Cartridge tape (QIC-24)
Note
MS-DOS Ver. 5.0 or later have a task swap function, but this task swap function cannot be used in this software.
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APPENDIX C EMBEDDED SOFTWARE
C.1 Real-time OS (2/2)
MX78K0 OS MX78K0 is a subset OS which is based on the ITRON specification. Supplied with the MX78K0 nucleus. MX78K0 OS controls tasks, events, and time. In task control, MX78K0 OS controls task execution order, and then perform the switching process to a task to be executed. Part Number: SxxxxMX78K0-
Remark xxxx and of the part number differs depending on host machine and OS, etc. Refer to the table below.
SxxxxMX78K0-
001 xx S01 xxxx 5A13 5A10
Product Outline Evaluation object Mass production object Source program
Cautions Use for experimental producing Use for mass production Purchasable only when purchasing mass production object
Host Machine PC-9800 series
Operating System MS-DOS Ver.3.30 to Ver.6.2Note
Supply Medium 3.5-inch 2HD 5-inch 2HD
7B13 7B10 3H15
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IBM PC/AT and compatible machine HP9000 series 300 HP9000 series 700 SPARCstation EWS4800 series (RISC)
See B.4
3.5-inch 2HC 5-inch 2HC
HP-UX (Rel7.05B) HP-UX (Rel9.01) SunOS (Rel4.1.1) EWS-UX/V(Rel4.0)
Cartridge tape (QIC-24) Digital audio tape (DAT) Cartridge tape (QIC-24)
3P16 3K15 3M15
Note
MS-DOS Ver. 5.0 or later have a task swap function, but this task swap function cannot be used in this software.
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APPENDIX C
EMBEDDED SOFTWARE
C.2 Fuzzy Inference Development Support System
FE9000/FE9200 Fuzzy Knowledge Data Preparation Tool Program supporting input of fuzzy knowledge data (fuzzy rule and membership function), editing (edit), and evaluation (simulation). FE9200 operates on Windows. Part Number: SxxxxFE9000 (PC-9800 series)
SxxxxFE9200 (IBM PC/AT and compatible machine)
FT9080/FT9085 Translator Program converting fuzzy knowledge data obtained by using fuzzy knowledge data preparation tool to the assembler source program for the RA78K/0. Part Number: SxxxxFT9080 (PC-9800 series)
SxxxxFT9085 (IBM PC/AT and compatible machine)
FI78K0 Fuzzy Inference Module FD78K0 Fuzzy Inference Debugger Program executing fuzzy inference. Fuzzy inference is executed by linking fuzzy knowledge data converted by translator. Part Number: SxxxxFI78K0 (PC-9800 series, IBM PC/AT and compatible machine) Support software evaluating and adjusting fuzzy knowledge data at hardware level by using in-circuit emulator. Part Number: SxxxxFD78K0 (PC-9800 series, IBM PC/AT and compatible machine)
Remark xxxx of the part number differs depending on the host machine or OS used.
SxxxxFE9000 SxxxxFT9080 SxxxxFI78K0 SxxxxFD78K0
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xxxx 5A13 5A10
Host Machine PC-9800 series
Operating System MS-DOS Ver.3.30 to Ver.6.2Note
Supply Medium 3.5-inch 2HD 5-inch 2HD
Note
MS-DOS Ver. 5.0 or later have a task swap function, but this task swap function cannot be used in this software.
SxxxxFE9200 SxxxxFT9085 SxxxxFI78K0 SxxxxFD78K0
xxxx 7B13 7B10
Host Machine IBM PC/AT and compatible machine
Operating System See B.4
Supply Medium 3.5-inch 2HC 5-inch 2HC
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APPENDIX D
REGISTER INDEX
APPENDIX D
REGISTER INDEX
D.1 Register Index (In Alphabetical Order with Respect to the Register Name) [A] A/D conversion result register (ADCR) ... 249 A/D converter input select register (ADIS) ... 253 A/D converter mode register (ADM) ... 251 Automatic data transmit/receive address pointer (ADTP) ... 412 Automatic data transmit/receive control register (ADTC) ... 416, 423 [E] 8-bit compare register (CR10, CR20) ... 207 8-bit timer mode control register (TMC1) ... 209 8-bit timer output control register (TOC1) ... 210 8-bit timer register 1 (TM1) ... 207 8-bit timer register 2 (TM2) ... 207 External interrupt mode register (INTM0) ... 184, 455 [I] Internal memory size switching register (IMS) ... 495 Interrupt mask flag register 0H (MK0H) ... 453, 470 Interrupt mask flag register 0L (MK0L) ... 453
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Interrupt request flag register 0H (IF0H) ... 452, 470 Interrupt request flag register 0L (IF0L) ... 452 Interrupt timing specification register (SINT) ... 276, 295, 314, 330, 356, 375, 388 [K] Key return mode register (KRM) ... 151, 471 [M] Memory expansion mode register (MM) ... 150, 476 [O] Oscillation stabilization time select register (OSTS) ... 484 [P] Port 0 (P0) ... 134 Port 1 (P1) ... 136 Port 2 (P2) ... 137, 139 Port 3 (P3) ... 141 Port 4 (P4) ... 142 Port 5 (P5) ... 143 Port 6 (P6) ... 144 Port mode register 0 (PM0) ... 146 Port mode register 1 (PM1) ... 146 Port mode register 2 (PM2) ... 146
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APPENDIX D
REGISTER INDEX
Port mode register 3 (PM3) ... 146, 183, 211, 242, 246 Port mode register 5 (PM5) ... 146 Port mode register 6 (PM6) ... 146 Priority specify flag register 0H (PR0H) ... 454 Priority specify flag register 0L (PR0L) ... 454 Processor clock control register (PCC) ... 158 Program status word (PSW) ... 102, 458 Pull-up resistor option register (PUO) ... 149 [S] Sampling clock select register (SCS) ... 185, 456 Serial bus interface control register (SBIC) ... 274, 280, 293, 313, 330, 341, 354, 374, 386 Serial I/O shift register 0 (SIO0) ... 269, 327 Serial I/O shift register 1 (SIO1) ... 412 Serial operating mode register 0 (CSIM0) ... 271, 277, 278, 291, 311, 330, 338, 339, 352, 372, 384 Serial operating mode register 1 (CSIM1) ... 415, 418, 419, 422 16-bit capture register (CR01) ... 177 16-bit compare register (CR00) ... 177 16-bit timer mode control register (TMC0) ... 180 16-bit timer output control register (TOC0) ... 182 16-bit timer register (TM0) ... 177 16-bit timer register (TMS) ... 209 Slave address register (SVA) ... 269, 327
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[T] Timer clock select register 0 (TCL0) ... 178, 240 Timer clock select register 1 (TCL1) ... 207 Timer clock select register 2 (TCL2) ... 224, 234, 244 Timer clock select register 3 (TCL3) ... 271, 330, 413 [W] Watch timer mode control register (TMC2) ... 227 Watchdog timer mode register (WDTM) ... 236
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APPENDIX D
REGISTER INDEX
D.2 Register Index (In Alphabetical Order with Respect to the Register Symbol) [A] ADCR ADIS ADM ADTC ADTP [C] CR00 CR01 CR10 CR20 CSIM0 CSIM1 [I] IF0H IF0L IMS INTM0 [K]
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: : : : :
A/D conversion result register ... 249 A/D converter input select register ... 253 A/D converter mode register ... 251 Automatic data transmit/receive control register ... 416, 423 Automatic data transmit/receive address pointer ... 412
: : : : : :
16-bit compare register ... 177 16-bit capture register ... 177 8-bit compare register ... 207 8-bit compare register ... 207 Serial operating mode register 0 ... 271, 277, 278, 291, 311, 330, 338, 339, 352, 372, 384 Serial operating mode register 1 ... 415, 418, 419, 422
: : : :
Interrupt request flag register 0H ... 452, 470 Interrupt request flag register 0L ... 452 Internal memory size switching register ... 495 External interrupt mode register ... 184, 455
KRM [M] MK0H MK0L MM [O] OSTS [P] P0 P1 P2 P3 P4 P5 P6 PCC PM0 PM1 PM2 PM3 PM5
:
Key return mode register ... 151, 471
: : :
Interrupt mask flag register 0H ... 453, 470 Interrupt mask flag register 0L ... 453 Memory expansion mode register ... 150, 476
:
Oscillation stabilization time select register ... 484
: : : : : : : : : : : : :
Port 0 ... 134 Port 1 ... 136 Port 2 ... 137, 139 Port 3 ... 141 Port 4 ... 142 Port 5 ... 143 Port 6 ... 144 Processor clock control register ... 158 Port mode register 0 ... 146 Port mode register 1 ... 146 Port mode register 2 ... 146 Port mode register 3 ... 146, 183, 211, 242, 246 Port mode register 5 ... 146
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APPENDIX D
REGISTER INDEX
PM6 PR0H PR0L PSW PUO [S] SBIC SCS SINT SIO0 SIO1 SVA [T] TCL0 TCL1 TCL2 TCL3 TM0 TM1 TM2 TMC0 TMC1
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: : : : :
Port mode register 6 ... 146 Priority specify flag register 0H ... 454 Priority specify flag register 0L ... 454 Program status word ... 102, 458 Pull-up resistor option register *** 149
: : : : : :
Serial bus interface control register ... 274, 280, 293, 313, 330, 341, 354, 374, 386 Sampling clock select register ... 185, 456 Interrupt timing specify register ... 276, 295, 314, 330, 356, 375, 388 Serial I/O shift register 0 ... 269, 327 Serial I/O shift register 1 ... 412 Slave address register ... 269, 327
: : : : : : : : : : : : :
Timer clock select register 0 ... 178, 240 Timer clock select register 1 ... 207 Timer clock select register 2 ... 224, 234, 244 Timer clock select register 3 ... 271, 330, 413 16-bit timer register ... 177 8-bit timer register 1 ... 207 8-bit timer register 2 ... 207 16-bit timer mode control register ... 180 8-bit timer mode control register ... 209 Watch timer mode control register ... 227 16-bit timer register ... 209 16-bit timer output control register ... 182 8-bit timer output control register ... 210
TMC2 TMS TOC0 TOC1
[W] WDTM : Watchdog timer mode register ... 236
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APPENDIX E
REVISION HISTORY
APPENDIX E
REVISION HISTORY
Major revisions by edition and revised chapters are shown below.
(1/4)
Edition 4th Major revisions from previous edition Revised Chapters General
PD78014Y subseries were added as applied devices.
Frequency of main system clock oscillator is changed from 8.38 MHz to 10.0 MHz. Item "After Reset" was added in section 2.1.1 "Normal operating mode pins". Cautions on pull-up resistors disconnection for P60 to P63 pins by mask option was added. Pin input/output circuit types were changed as follows. Change: Type 5-B to Type 5-E, Type 9-B to Type 11 Addition: Type 16 Memory size switching register is incorporated in all applied devices, not only in the PD78P014. Cautions on using port 1 as A/D converter input was added. Cautions on port mode register setting when port 2 is used in the SBI mode was added. Cautions on port mode register setting was added. Cautions on pull-up resistor option register when port is used as dual-function pin was added. Cautions on CR00 setting was added. Timing chart for square-wave output operation was added. Cautions on using 8-bit timer registers 1 and 2 as a 16-bit timer register was added.
CHAPTER 2 PIN FUNCTION
CHAPTER 3 CPU ARCHITECTURE CHAPTER 4 PORT FUNCTIONS
CHAPTER 6 16-BIT TIMER/EVENT COUNTER CHAPTER 7 8-BIT TIMER/EVENT COUNTER
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Interval times of interval timer were changed. Block diagram for watchdog timer was corrected. Cautions on overflow time when the watchdog timer is cleared by setting bit 7 (RUN) of WDTM to 1 was added. Condition under which clock output cannot be used was added.
CHAPTER 8 WATCH TIMER CHAPTER 9 WATCHDOG TIMER
CHAPTER 10 CLOCK OUTPUT CONTROL CIRCUIT
Condition under which buzzer output cannot be used was added.
CHAPTER 11 BUZZER OUTPUT CONTROL CIRCUIT
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APPENDIX E
REVISION HISTORY
(2/4)
Edition 4th Major revisions from previous edition Format of the A/D converter mode register was changed. Section 12.4.2 "Input voltage and conversion results" was added. Following items were added in section 12.5 "Cautions on A/D Converter". (5) AVREF pin input impedance (6) Interrupt request flag of A/D conversion end (INTAD) (7) AVDD pin (8) Interrupt request flag of A/D conversion (ADIF) Block diagram for serial interface channel 0 was changed. Format of the serial operating mode register 0 was changed. Serial bus interface control register format was changed. Timing charts for various signals in the SBI mode and flag operations in SBIC register were changed. Item (e) Procedure to judge whether slave device is in the busy state or not when device is in the master mode was added in section 13.4.2 "Cautions on SBI mode". Section 13.4.4 "I2C bus mode operation" was added. Block diagram for serial interface channel 1 was changed. Format of the serial operating mode register 1 was changed. Timing chart for 3-wire serial I/O mode was corrected. Timing chart and flowchart for basic transmit/receive mode were corrected. Flowchart for repeat transmission mode was corrected. Timing chart when using busy control option was corrected. Timing chart when using busy & strobe control option was corrected.
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Revised Chapters CHAPTER 12 A/D CONVERTER
CHAPTER 13 SERIAL INTERFACE CHANNEL 0
CHAPTER 14 SERIAL INTERFACE CHANNEL 1
Cautions on TMIF4 flag of IF0L register was added. Cautions on using port 0 as output port was added. Item "Watch timer" was added in Table 17-1 "HALT Mode Operating Status".
CHAPTER 15 INTERRUPT FUNCTION CHAPTER 17 STANDBY FUNCTION
Description of NMIS was added in description of RETI instruction.
CHAPTER 20 INSTRUCTION SET
APPENDIX B, "EMBEDDED SOFTWARE" was added.
APPENDIX B EMBEDDED SOFTWARE
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APPENDIX E
REVISION HISTORY
(3/4)
Edition 5th Major revisions from previous edition Revised Chapters General
PD78011B(A), 78012B(A), 78013(A), 78014(A) were added as applied devices.
Cautions on rewriting the timer clock select registers 0 to 2 (TCL0 to TCL2) to other data was added. Watchdog timer count clocks (Inadvertent program loop detection period) selected by TCL20 to TCL22 of the timer clock select register 2 (TCL2) were changed.
Recommended connection of unused pins P04, P40 to P47 and P60 to P63 were changed as follows. P04: Connect to VSS Connect to VDD or VSS P40 to 47, P60 to 63: Connect to VDD or VSS Connect to VDD
CHAPTER 3 PIN FUNCTION (PD78014 Subseries) CHAPTER 4 PIN FUNCTION (PD78014Y Subseries)
List of maximum time required for CPU clock switchover were corrected.
CHAPTER 7 CLOCK GENERATOR
Descriptions in section 16.4.5 "I2C bus mode operation" were changed. Following subsections were added in section 16.4.6 "Cautions on Use of I2C Bus Mode". (3) Slave wait release (slave reception), (4) Reception completion processing by a slave Section 16.4.7 "Restrictions on Use of I2C Bus Mode" was added. Sections 20.2 "Operation Codes" and 20.3 "Descriptions of Instructions" in previous edition were deleted. 6th
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78014Y Subseries)
CHAPTER 23 INSTRUCTION SET CHAPTER 11 WATCHDOG TIMER CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78014Y Subseries)
Figure 11-3, "Watchdog Timer Mode Register Format" was changed and cautions for the figure were added. Cautions on serial I/O shift register 0 (SIO0) of the PD78014 subseries were added. Figure 16-45, "Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait)" was corrected. Figure 16-46, "Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait)" was corrected. The following products were added. IE-78000-R-A, IE-70000-98-IF-B, IE-70000-98N-IF, IE-70000-PC-IF-B, IE-78000-R-SV3, ID78K0 The development of the following product was completed. IE-78014-R-EM-A An explanation for how to upgrade in-circuit emulator to IE-78000-R-A was added. The version numbers of the supported operating systems were renewed.
APPENDIX A DEVELOPMENT TOOLS
APPENDIX A DEVELOPMENT TOOLS and APPENDIX B EMBEDDED SOFTWARE
545
APPENDIX E
REVISION HISTORY
(4/4)
Edition 7th Major revisions from previous edition P20, P21, P23 to P26 Block Diagrams, P22 and P27 Block Diagrams, and P30 to P37 Block Diagrams were corrected. Figure 9-10 and 9-13, "Square Wave Output Operation Timings" were added. Revised Chapters CHAPTER 6 PORT FUNCTIONS CHAPTER 9 8-BIT TIMER/EVENT COUNTER Caution was added in section 15.1 "Serial Interface Channel 0 Functions". Caution was added in section 15.3 "Serial Interface Channel 0 Control Register (2) Serial operating mode register 0 (CSIM0)". Cautions were added in section 15.4.3 "(2) (a) Bus release signal (REL), (b) Command signal (CMD), (11) Cautions on SBI mode". Caution was added in section 16.1 "Serial Interface Channel 0 Functions". Caution was added in section 16.3 "Serial Interface Channel 0 Control Register (2) Serial operating mode register 0 (CSIM0)". Cautions were added in section 16.4.3 "(2) (a) Bus release signal (REL), (b) Command signal (CMD), (11) Cautions on SBI mode". Item "(3) MSB/LSB switching as the start bit" was added in section 17.4.2 "3-wire serial I/O mode operation". (3) (d) Busy control option, (e) Busy & strobe control option, and (f) Bit slippage detection function in section 17.4.3 of the former edition were changed to (4) Synchronization control and the description was improved. Caution was added in Table 22-1, "Differences between PD78P014, 78P014Y, and Mask ROM Version".
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CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (PD78014 Subseries)
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD78014Y Subseries)
CHAPTER 17 SERIAL INTERFACE CHANNEL 1
CHAPTER 22
PD78P014, 78P014Y
APPENDIX A DIFFERENCES BETWEEN
APPENDIX A, "DIFFERENCES BETWEEN PD78014, 78014H, AND 78018F SUBSERIES" was added.
PD78014, 78014H, AND
78018F SUBSERIES Windows compatible 5-inch FD products was erased in APPENDIX B DEVELOPMENT TOOLS. The following products were changed from "Under development" to "Developed". * IE-78000-R-A * ID78K0 APPENDIX B DEVELOPMENT TOOLS
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APPENDIX E
REVISION HISTORY
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